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This adds a INTEL_GMA_VBT_HAVE_DATA_FILE Kconfig option for the path
to point to the mainboard dir and to select
INTEL_GMA_ADD_VBT_DATA_FILE by default.
Change-Id: I730cb0737945631e2d5379a9e26b8c039ec6dc49
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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* Remove 2nd software stack in pc80 drivers directory.
* Create TSPI interface for common usage.
* Refactor TSS / TIS code base.
* Add vendor tss (Cr50) directory.
* Change kconfig options for TPM to TPM1.
* Add user / board configuration with:
* MAINBOARD_HAS_*_TPM # * BUS driver
* MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2
* Add kconfig TPM user selection (e.g. pluggable TPMs)
* Fix existing headers and function calls.
* Fix vboot for interface usage and antirollback mode.
Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Besides the FSP codepath, Sandy Bridge has two codepaths, one native
and one in the form of a binary. This allows the use of the binary.
This can be useful to find flaws in the native raminit.
The native raminit is still selected by default.
Change-Id: I2d71fb7bc5f7b0976157be146c0e4c39a3ed5602
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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All affected boards did the same USE_NATIVE_RAMINIT distinction or
actually selected USE_NATIVE_RAMINIT. Also update autoport.
Change-Id: I924c43cec1e36e84db40e4b8e1dd0e05cad2b978
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20813
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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Change-Id: I8b02596b116c0b164e83e7b02449c547224a50a6
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/20330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This timeout is probably needed on all devices with Lenovo H8 embedded
controllers so set the default there.
Change-Id: I830ab1894f7c0f10f55c82e398becf44d810852d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18274
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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The h8s needs around 3s to respond to ps2 commands
Change-Id: I0cf01969975b8dd3839eadf90cb2dac0f1eaafc4
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/16505
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
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Set MMCONF_BASE_ADDRESS to 0xf8000000.
It was already done for some boards, but not all.
The sandybridge chipset code assumes 64 pci buses behind MMCONF.
Therefore, only 64MiB of physical address space is required.
Increasing the address allows to use additional 128MiB of MMIO
space and to use the Intel IGD and a PEG at the same time.
Previously it wasn't possible to use both at the same time,
as two 256MiB areas won't fit into MMIO space.
Test system:
* Gigabyte GA-B75M-D3H
* Intel Pentium CPU G2130
* Onboard GPU Intel IvyBridge Desktop
* PEG GPU AMD RV770
Change-Id: I3bf72439056c8089ada6899bb0605e5cd9d89cd6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14096
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
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Sandy and Ivy Bridge processors use the same socket, and a mainboard
with the socket can support both types of CPUs. However, they use
different native graphics init code for LVDS and cause a crash if
running the wrong code.
This change detects the CPU type and then selects the right code to
run. It will add some more code in ramstage. It also merges the
{SANDY,IVY}BRIDGE_LVDS symbol to one SANDYBRIDGE_IVYBRIDGE_LVDS.
Tested on a Lenovo T520 with i7-2630qm and i7-3720qm
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Change-Id: I4624759f9c92d56d547db1ab4b9a1d611a182a91
Reviewed-on: https://review.coreboot.org/12087
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Tested-by: build bot (Jenkins)
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Tested by making lenovo x230 configurable despite pretty MRC bugs.
Change-Id: Ia2a123f24334f5cd5f42473b7ce7f3d77c0e65b7
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13658
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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In the same time remove few native gfx options which were improperly set
and only added dead code to the binary.
Change-Id: I4ed3fec03a1655ae0a779c3aa3845de273cb12e1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13649
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
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The ThinkPad X220i is essentially identical to the ThinkPad X220 but it
has a Sandybridge i3 (instead of a Sandybridge i5/i7) CPU and the
VGA_BIOS_ID differs. Thus, support is added by using the X220 mainboard
directory and setting the VGA_BIOS_ID in Kconfig.
Change-Id: I33345a099c617e8c87a1de64b7254b7e7716ca90
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Reviewed-on: https://review.coreboot.org/13594
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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If any path in a method returns a value, IASL expects that all paths
within that method will return a value.
Presumably the MKHP method wouldn't get called unless there were a
pending event, but if no event is found, return a zero.
Fixes IASL warning:
dsdt.aml 1785: Method (MHKP, 0, NotSerialized)
Warning 3115 - ^ Not all control paths return a value (MHKP)
This was the only IASL warning in most lenovo mainboards.
Change-Id: Id93dcc4a74bd4c18b78f1dde821e7ba0f3444da3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12517
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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We've actually got more warnings now than when I first tested IASL
warnings as errors. Because of this, I'm adding it with the option
to have it disabled, in hopes that things won't get any worse as we
work on fixing the IASL warnings that are currently in the codebase.
- Enable IASL warnings as errors
- Disable warnings as errors in mainboards that currently have warnings.
- Print a really obnoxious message on those platforms when they build.
***** WARNING: IASL warnings as errors is disabled! *****
***** Please fix the ASL for this platform. *****
Change-Id: If0da0ac709bd8c0e8e2dbd3a498fe6ecb5500a81
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10663
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This is a sad story. We have three different code paths for
sandybridge and ivybridge: proper native path, google MRC path, and,
everyone's favorite: Intel FSP path. For the purpose of this patch,
the FSP path lives in its own little world, and doesn't concern us.
Since MRC was first, when native files and variables were added, they
were suffixed with "_native" to separate them from the existing code.
This can cause confusion, as the suffix might make the native files
seem parasitical.
This has been bothering me for many months. MRC should be the
parasitical path, especially since we fully support native init, and
it works more reliably, on a wider range of hardware. There have been
a few board ports that never made it to coreboot.org because MRC would
hang.
gigabyte/ga-b75m-d3h is a prime example: it did not work with MRC, so
the effort was abandoned at first. Once the native path became
available, the effort was restarted and the board is now supported.
In honor of the hackers and pioneers who made the native code
possible, rename things so that their effort is the first class
citizen.
Change-Id: Ic86cee5e00bf7f598716d3d15d1ea81ca673932f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11788
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
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Every Lenovo Thinkpad includes a Trusted Platform Module, so we can enable
it for the sandy-/ivybridge platforms.
Change-Id: Icda443ba88c2a49a0033014ce7710dd607fa15dc
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: http://review.coreboot.org/10411
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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These boards don't have Super I/O's, rather they use Embedded
Controllers instead. No need to confuse with Super I/O related
stuff showing up in menuconfig.
Change-Id: I4922319daf7920bf5331b5bce05ded0d9a31a69b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7986
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
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Change-Id: Ide09e129fd9400eb20f9b7bb3cd0e5d6d271e372
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8176
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This config is used only to generate PIRQ table. If no such table is
supplied there is no need for config.
Change-Id: I537d440f53019a6bf7f190446074e75e7420545a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7566
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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Southbridge already selects it, no need to repeat.
Change-Id: I9a5ad553f48e30103371cc2d896168ae4abfb8ef
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7570
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I76577cc3739f23d392d077db5a5edfdbdbe8fb1e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7466
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
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Change-Id: Id0aecbd3e45bdf9661168ebd0e55f17dc6febaaa
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7203
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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Change-Id: Ia4060831236d72f880eeff6263ada40cf195fb12
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7180
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
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Part number is used only for coreboot ROM identification and
in coreboot tables. Rather than guessing the P/N, just use readable name.
SMBIOS uses information from EEPROM and so isn't affected.
Change-Id: I33534c3acb83f20d5b493c82bfc98896bf64ff1a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7177
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
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Change-Id: I54955fa44d126b7a3d382f57b4aa0dac01688104
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7129
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: I179a4cede2f826f72a400208748798737216c01a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7071
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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Change-Id: I9366dded98bf15f6da44ce893dd10698ba09fd55
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6820
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: Ic213948e4d31457dda9b9f2d5a4f92cd34d1e57d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6757
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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