coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-08-26	soc/intel: Use common romstage code	Kyösti Mälkki
2019-08-18	cpu/intel: Enter romstage without BIST	Kyösti Mälkki
2019-06-06	sb/intel/i82801gx: Detect if the southbridge supports AHCI	Arthur Heymans
2019-06-05	mb/*/devicetree.cb: Remove unavailable PCIe ports	Arthur Heymans
2019-04-13	sb/intel/i82801gx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB	Patrick Rudolph
2019-03-13	{mb,nb/pineview}/*.asl: Remove unneeded include i82801gx.h	Elyes HAOUAS
2019-03-01	device/pci: Fix PCI accessor headers	Kyösti Mälkki
2019-02-07	src: Remove unused include device/pnp_def.h	Elyes HAOUAS
2019-01-28	mb/lenovo/thinkcentre_a58: Extend mb name	Arthur Heymans
2019-01-10	mb: Move timestamp_add_now to northbridge x4x	Elyes HAOUAS
2019-01-09	cpu/intel: Use the common code to initialize the romstage timestamps	Arthur Heymans
2019-01-08	sb/intel/i82801gx: Autodisable functions based on devicetree	Arthur Heymans
2018-12-28	arch/x86: Drop spurious arch/stages.h includes	Kyösti Mälkki
2018-12-19	smsc/sch5147: Implement ACPI handling of a few LDN	Arthur Heymans
2018-12-19	mb/lenovo/thinkcentre_a58: Add mainboard	Arthur Heymans