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Discussed in CB:36093, in the past many lenovo boards need to declare
an empty h8_mainboard_init_dock() to satisfy h8.c.
Now the confusing H8_DOCK_EARLY_INIT might be retired, and if a
mainboard needs dock init (done with h8_mainboard_init_dock() in the
past) in ramstage, (discussed in CB:4294 where H8_DOCK_EARLY_INIT is
introduced) it can just do it in its own chip_ops.enable_dev function.
Tested on X200. Testing on other affected targets may be necessary.
Change-Id: I5737406d1f6cb6e91b2e2fa349a206a3dba988d1
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I36095422559e6c160aa57f8907944faa4c192dee
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch creates a common instance of sleepstates.asl inside intel common
code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to
refer sleepstates.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
S0/S3/S4/S5 entries after booting to OS.
Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This sets up some common default LPC decode ranges in a common place.
This may set up more decode ranges than needed but that typically does
not hurt. Mainboards needing additional ranges can do so in the
mainboard pch_enable_lpc hook.
Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Port_List is an array of 8 elements, and GCC 9 is warning that there
are no 'others' when all 8 elements are explicitly initialized, which is
causing the build to fail. Remove the 'others => Disabled' clause to
silence this.
Change-Id: Id082e7a76641438f3fb4c4d976dbd254a7053473
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34918
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The processor P_BLK doesn't support throttling. This behaviour could be
emulated with SMM, but instead just update the FADT to indicate no support
for legacy I/O based throttling using P_CNT.
We have _PTC defined in SSDT, which should be used in favour of P_CNT by
ACPI aware OS, so this change has no effect on modern OS.
Drop all occurences of p_cnt_throttling_supported and update autoport
to not generate it any more.
Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Build of the entire smm-class is skipped if we have
HAVE_SMI_HANDLER=n.
Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set up generic decode ranges based on the devicetree settings.
Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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* Select ONBOARD_VGA_IS_PRIMARY in driver/lenovo/hybrid_graphics to fix
disabling iGPU in 'Dual Graphics' on Lenovo T430.
* Remove ONBOARD_VGA_IS_PRIMARY in mainboards that already select
DRIVERS_LENOVO_HYBRID_GRAPHICS.
Change-Id: I6594fbb957c9a8135fe670d38b5755adf29d2dff
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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These boards don't need a default FMAP. Moreover, having a default FMAP
disables automatic integration of optional regions like `CONSOLE`.
Also, these files contain an error: `COREBOOT` isn't placed at the top
of the image. Resulting in default builds without a reset vector ;)
Change-Id: If6331e19955034c02828e88902a5934c34d3e784
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33110
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Unify thermal handling across Lenovo boards (except g505, which is
different). Namely, do the following:
* Move thermal levels from acpi_tables to thermal.h (and create if
necessary).
* Don't use board-specific ifdef guards.
* Set thermal levels using dedicated acpi_update_thermal_table function
as almost all Lenovo boards do.
* Update list of authors in comments. Merge all author's entries.
* Minor whitespace and formatting.
This makes diff -ruw between the Lenovo boards smaller.
Change-Id: If569f67c932b7fbf14893b890a5588df4994daeb
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29659
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable VBOOT support on all devices that have a 8 MiB flash, using a
single RW_MAIN_A partition, allowing the use of tianocore payload in
both RW_MAIN_A and WP_RO.
* Add VBNV section to cmos.layout
* Add FMAP for VBOOT and regular boot
* Select Kconfigs for VBOOT
* Enable VBOOT_SLOTS_RW_A by default
Also build test VBOOT on Lenovo T420.
Tested on Lenovo T520 using Icb7b263ed86551cc53e1db7babccaca6b3ae2fe6.
Change-Id: Icb7b263ed86551cc53e1db7babccaca6b3ae2fe6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Mark all known PCIe root ports as ExpressCard slot.
Tested on Lenovo T520.
Change-Id: I43fb481512a54ee054c6fd0189053028fb3c3ec2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32309
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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References to MAINBOARD_PCI_SUBSYSTEM_{DEVICE_ID,VENDOR_ID} were removed
in commits
dbd3132 sb/intel/{i82801g/i/j,bd82x6x}: Make use of generic set_subsystem()
00bb441 sb/intel/lynxpoint: Remove PCI bridge function
Change-Id: I72bba8406eea4a264e36cc9bcf467cf5cfbed379
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32107
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There are two known reverse-engineered ways to manage battery
thresholds.
This patch implements them and adds a way to enable them for
different mainboards.
Tested on W530 with 4.18.3-gentoo kernel and X220 with 4.20.11.
Works fine with new Linux userspace API for controlling battery
thresholds, available since 4.17.
(/sys/class/power_supply/BAT0/charge_(start|stop)_threshold).
The new API is supported by TLP (you might need to set NATACPI_ENABLE=1
in /etc/tlp.conf).
tpacpi-bat works fine too.
Signed-off-by: Alexey Kharlamov <der@2-47.ru>
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Change-Id: I2a90f9e9b32462b8a5e9bc8d3087ae0fea563ea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/23178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: I91158452680586ac676ea11c8589062880a31f91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31692
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.
Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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need it
Hide "Add gigabit ethernet firmware" option for boards that do not
use GbE firmware in GbE section.
The option is now hidden by default and can be reenabled on a
per-board basis by selecting MAINBOARD_USES_IFD_GBE_REGION in the
mainboards Kconfig.
The following boards seem to use this:
mb/roda/rv11
mb/ocp/wedge100s
mb/ocp/monolake
mb/lenovo/x230
mb/lenovo/x220
mb/lenovo/x201
mb/lenovo/x200
mb/lenovo/t530
mb/lenovo/t520
mb/lenovo/t430s
mb/lenovo/t430
mb/lenovo/t420s
mb/lenovo/t420
mb/lenovo/t400
mb/kontron/ktqm77
mb/intel/saddlebrook
mb/intel/kblrvp
mb/intel/dg43gt
mb/intel/dcp847ske
mb/intel/coffeelake_rvp
mb/intel/camelbackmountain_fsp
mb/hp/revolve_810_g1
mb/hp/folio_9470m
mb/hp/compaq_8200_elite_sff
mb/hp/8770w
mb/hp/8470p
mb/hp/8460p
mb/hp/2760p
mb/hp/2570p
mb/google/sarien
mb/facebook/watson
mb/compulab/intense_pc
mb/asus/maximus_iv_gene-z
The boards were identified by looking at devicetree.cb, but this
list is possibly still incomplete.
Change-Id: Ibfb07902ad93fe5ff2bd4f869abcf6579f7b5a79
Signed-off-by: Jan Tatje <jan@jnt.io>
Reviewed-on: https://review.coreboot.org/c/30790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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With the memory controller the separate sockets becomes a useless
distinction. They all used the same code anyway.
UNTESTED: This also updates autoport.
Change-Id: I044d434a5b8fca75db9eb193c7ffc60f3c78212b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31031
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is a merely cosmetic change.
Change-Id: If36419fbee9628b591116604bf32fe00a4f08c17
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
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Libgfxinit provides a better alternative to the native C init. While
libgfxinit mandates an ada compiler, we want to encourage use of it
since it is in much better shape and is actually maintained.
This way libgfxinit also gets build-tested by Jenkins.
Change-Id: Ic6678d3455f1116e7e67a67b465a79df020b2399
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/27532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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ENABLE_VMX is CPU specific and it is already enabled here:
src/cpu/intel/common/Kconfig
Change-Id: I130738aa3758a9212bab10f90edb7b2ab6830597
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Re-write the UAO handling code as it had stopped working (#171)
(the flag was not getting read from the RTC properly in SMM)
Remove the SMM code as it's not needed (but EC flag won't be set
upon entering S3 now)
Set the EC flags on boot the same way other flags are set
Document bitwise operators for clarity
Propagate changes to other Thinkpads
(updated X201 to have 2 bits for the flag as it only had 1)
Per Nicola Corna's previous commits, 0x0d is set for "AC only"
"AC only" does exhibit different behaviour - the USB port is
turned on a few seconds after entering S3, rather than < 1 sec,
regardless of AC status
Tested on X220
Change-Id: If812cd1ef8fb1a24d7fadbe834f574b40cbcd56a
Signed-off-by: Nathaniel Roach <nroach44@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: David Guckian
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Change-Id: Ibdff50761a205d936b0ebe067f418be0a2051798
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hellsenberg <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Guckian
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Field 'OEMID' & "OEM Table ID" are related to DSDT table
not to mainboard.
So use macro to set them respectvely to "COREv4" and
"COREBOOT".
Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
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DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version.
This will cause the AML interpreter to use 32-bit integers and math
if the version is 1, and 64-bit if the version is >=2.
Current spec version is 2 for ACPI 6.2-a.
Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29626
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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IGD display handling was rewritten with commit dd2bc3f8 with Change-Id
I556769e5e28b83e7465e3db689e26c8c0ab44757 ("igd.asl rewrite"). These
comments were removed as well (with some accidentally left behind).
Let's remove them and those who were introduced later with new ports.
Change-Id: I8d3e12d0c3b03b0de38e65f36b94ed706fbf893c
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29271
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ib359e4039f87bb87faac040f24f70cc0988c0ea8
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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L520 and T420 should also use it - platforms are very similar to t420s
and t530. Z61t is based on T60/X60, X131e is based on X230 so commit
with Change-Id I13c08b8c6b1bf0f3deb25a464b26880d8469c005 should be
applied as well.
All four platforms are using ec/lenovo/h8 embedded controller.
Change-Id: Ib177f024871e82979dd430da86f1551aef14d446
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add CMOS option that allows to use both integrated and discrete GPU.
Tested on ThinkPad W530.
Change-Id: I8842fef0fa1235eb91abf6b7e655ed4d8598adc7
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Reviewed-on: https://review.coreboot.org/28393
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Used default console log level is 7 in src/console/Kconfig.
So let cmos.default use the same level as default.
Change-Id: Ia39ee457a8985142f6e7a674532995b11cb52198
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Since only a handful of boards have descriptor blobs in the tree, it makes no
sense to have `HAVE_IFD_BIN` enabled by default then disabled on each mainboard.
This patch flips the default value of said variable, rendering all current
overrides unnecessary. The few boards which have an IFD in the blobs repo use
`select HAVE_IFD_BIN` to enable adding the IFD by default.
Since `HAVE_ME_BIN` depends on `HAVE_IFD_BIN`, the former has been removed
alongside the latter, and has been added to the boards with a ME blob as
`select HAVE_ME_BIN`.
Both `HAVE_IFD_BIN` and `HAVE_ME_BIN` have been removed from autoport as well.
Change-Id: I330c4886f8bea4b1a8ecad6505a0e5cc381654d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/27218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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In the end it does not look like RCBA register offsets are fully
compatible over southbridges.
This reverts commit d2d2aef6a3222af909183fb96dc7bc908fac3cd4.
Is squashed with revert of "sb/intel/common: Fix conflicting OIC
register definition" 8aaa00401b68e5c5b6c07b0984e3e7c3027e3c2f.
Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Shuffle words and drop the _DATA_FILE suffix.
Change-Id: I0b0d50ea729e5580c0bc7b43f250ff387ce59cfc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: If1f032d097224a1102ba29d8d45dce46aad3a91a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This adds a INTEL_GMA_VBT_HAVE_DATA_FILE Kconfig option for the path
to point to the mainboard dir and to select
INTEL_GMA_ADD_VBT_DATA_FILE by default.
Change-Id: I730cb0737945631e2d5379a9e26b8c039ec6dc49
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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* Remove 2nd software stack in pc80 drivers directory.
* Create TSPI interface for common usage.
* Refactor TSS / TIS code base.
* Add vendor tss (Cr50) directory.
* Change kconfig options for TPM to TPM1.
* Add user / board configuration with:
* MAINBOARD_HAS_*_TPM # * BUS driver
* MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2
* Add kconfig TPM user selection (e.g. pluggable TPMs)
* Fix existing headers and function calls.
* Fix vboot for interface usage and antirollback mode.
Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This change adds and updates headers in all of the mainboard files that
had missing or unrecognized headers. After this goes in, we can turn on
lint checking for headers in all mainboard directories.
Change-Id: Ibe038a8f7468253b21fd2ac90c045d0c9cc89dfc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add the Video Bios Table to improve user experience when running
coreboot's blob free graphics init.
As it's not a binary blob it should not be added to the blobs repo.
This is taken from vendor BIOS and contains purely documented
configuration data, so it should not be subjected to copyright.
Extracted using intelvbttool with applied patch
I8cbde042c7f5632f36648419becd23e248ba6f76 "util/intelvbttool: Rewrite tool"
Change-Id: I15573ddd37ee9738df1f7178f967131687a50f48
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/25926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Use of device_t has been abandoned in ramstage.
Change-Id: Ic044fc074c43db683fcd85ce92a36a8c5a464a67
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This moves the sandybridge both smm setup and smihandler code to a
common place.
Tested on Thinkpad X220, still boots, resume to and from S3 is fine
so smihandler is still working fine.
Change-Id: I28e2e6ad1e95a9e14462a456726a144ccdc63ec9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Many generations of Intel hardware have identical code concerning the
RCBA.
Change-Id: I33ec6801b115c0d64de1d2a0dc5d439186f3580a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Fix the values that were off by one.
This was discovered when using postcar stage that prints with
debuglevel BIOS_NEVER.
Change-Id: I73a077950ed0dc735d89c9747a8da0a25f30822d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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|
Most affected boards set the function disabled (FD) register to an
arbitrary state dumped from systems running the vendor BIOS. This
makes it impossible to enable the devices in devicetree and a pretty
big mess of course because nobody cared to keep the register in sync
with the devicetree.
To get completely rid of most of the writes to FD, move setting of
PCH_DISABLE_ALWAYS into the southbridge code where it belongs.
Change-Id: Ia2a507cbcdf218d09738e2e16f0d3ad1dcf57b8b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/23255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hal Martin <hal.martin+coreboot@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bill XIE <persmule@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Enable change Ic6b8ce4a9db50211a9c26221ca10105c5a0829a0
(sb/intel/common: Automatically generate ACPI PIRQ) for BD82X6X.
This generates the main ACPI _PRT table automatically based on the
chipset registers.
Tested on Intel NUC DCP847SKE with Linux 4.13.14:
$ cat /proc/interrupts
CPU0 CPU1
0: 23 0 IO-APIC 2-edge timer
8: 1 0 IO-APIC 8-edge rtc0
9: 0 0 IO-APIC 9-fasteoi acpi
19: 86 0 IO-APIC 19-fasteoi ehci_hcd:usb1
23: 0 0 IO-APIC 23-fasteoi i801_smbus
[...MSI and other interrupts skipped...]
Log messages:
ACPI_PIRQ_GEN PCI: 00:02.0: pin=1 pirq=1
ACPI_PIRQ_GEN PCI: 00:1b.0: pin=1 pirq=1
ACPI_PIRQ_GEN PCI: 00:1c.0: pin=1 pirq=2
ACPI_PIRQ_GEN PCI: 00:1c.1: pin=2 pirq=6
ACPI_PIRQ_GEN PCI: 00:1c.2: pin=3 pirq=4
ACPI_PIRQ_GEN PCI: 00:1d.0: pin=1 pirq=4
ACPI_PIRQ_GEN PCI: 00:1f.2: pin=1 pirq=2
ACPI_PIRQ_GEN PCI: 00:1f.3: pin=2 pirq=8
ACPI_PIRQ_GEN PCI: 00:04.0: pin=1 pirq=1
Generated _PRT:
Scope (\_SB.PCI0)
{
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
{
If (PICM)
{
Return (Package (0x09)
{
Package (0x04)
{
0x0002FFFF,
0x00000000,
0x00000000,
0x00000010
},
Package (0x04)
{
0x001BFFFF,
0x00000000,
0x00000000,
0x00000010
},
Package (0x04)
{
0x001CFFFF,
0x00000000,
0x00000000,
0x00000011
},
Package (0x04)
{
0x001CFFFF,
0x00000001,
0x00000000,
0x00000015
},
Package (0x04)
{
0x001CFFFF,
0x00000002,
0x00000000,
0x00000013
},
Package (0x04)
{
0x001DFFFF,
0x00000000,
0x00000000,
0x00000013
},
Package (0x04)
{
0x001FFFFF,
0x00000000,
0x00000000,
0x00000011
},
Package (0x04)
{
0x001FFFFF,
0x00000001,
0x00000000,
0x00000017
},
Package (0x04)
{
0x0004FFFF,
0x00000000,
0x00000000,
0x00000010
}
})
}
Else
{
Return (Package (0x09)
{
Package (0x04)
{
0x0002FFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKA,
0x00000000
},
Package (0x04)
{
0x001BFFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKA,
0x00000000
},
Package (0x04)
{
0x001CFFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKB,
0x00000000
},
Package (0x04)
{
0x001CFFFF,
0x00000001,
\_SB.PCI0.LPCB.LNKF,
0x00000000
},
Package (0x04)
{
0x001CFFFF,
0x00000002,
\_SB.PCI0.LPCB.LNKD,
0x00000000
},
Package (0x04)
{
0x001DFFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKD,
0x00000000
},
Package (0x04)
{
0x001FFFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKB,
0x00000000
},
Package (0x04)
{
0x001FFFFF,
0x00000001,
\_SB.PCI0.LPCB.LNKH,
0x00000000
},
Package (0x04)
{
0x0004FFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKA,
0x00000000
}
})
}
}
}
Change-Id: I832a86925283d61b64b8268246d9e6f11994c120
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/22859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
There have been discussions about removing this since it does not seem
to be used much and only creates troubles for boards without defaults,
not to mention that it was configurable on many boards that do not
even feature uart.
It is still possible to configure the baudrate through the Kconfig
option.
Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Add support for BDC detection, based on the schematics for each board.
Support for boards without schematics needs further testing.
Needs test on all boards.
Change-Id: If33ef88fb808f36b050393fa83eb1b541ce936b9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
|
|
Add a new Kconfig option to ignore memory fuses that limit the
maximum DRAM frequency to be used. The option is disabled by
default and should only enabled by experienced users as it
might decrease system stability or prevent a successful RAM
training.
Remove conflicting devicetree settings.
Change-Id: I35dd78a02bcaafce8ba522d253c795d7835bacae
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nicola Corna <nicola@corna.info>
|
|
Get rid of old hybrid graphics driver and use the new one.
1. Disable IGD and PEG in early romstage.
The PEG port will get disabled on devices that do not have a
discrete GPU. The power savings are around ~1Watt.
The disabled IGD does no longer waste GFX stolen memory.
2. Get rid of PCI driver
The Nvidia GPU can be handled by the generic PCI driver and allows
to use the ACPI _ROM generator for Switchable graphics.
3. Settings are stored in devicetree.
One driver for all Lenovo hybrid graphics capable devices.
4. Add support for Thinker1 GPU power handling.
Only boards that do use reference design 2012 are known to be
supported. Needs test on boards that do you use reference design 2013.
Should reduce idle power consumption when using IGD by ~5Watt.
Tested on Lenovo T430 without DGPU. PEG port is disabled.
Needs test on all devices.
Change-Id: Ibf18b75e8afe2568de8498b39a608dac8db3ba73
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
All affected boards did the same USE_NATIVE_RAMINIT distinction or
actually selected USE_NATIVE_RAMINIT. Also update autoport.
Change-Id: I924c43cec1e36e84db40e4b8e1dd0e05cad2b978
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20813
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
|
|
Change-Id: I8febb8d74e2463622cab0313c543ceebec71fdf4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Port commit f1395d82: "ec/lenovo/h8: Add USB Always On"
to other Thinkpad boards, as it seems to work fine on all
generations.
Change-Id: I6dcbfaae2a444d9a679ecb64a87dc2a59b8fd281
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
Fix for all Sandy-Bridge and Ivy-Bridge devices.
Remove unused option "hyper_threading".
Increase CMOS checksum range to cover all user adjustable settings.
Change-Id: I02f7af13d9c82d7f531d4b49b3bc0e5a20c14b55
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Get rid of mainboard_io_trap_handler.
The only purpose is to enable tp-smapi, but is already done on all
boards in h8_enable, as of devicetree setting config0.
Change-Id: I33fd829a7e34aefa8f76ca6020cc8e802f7aab17
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
All those boards do not have a serial port.
Don't attempt to decode the COMA/COMB IO range.
Change-Id: Ide7e818f87e70e3f559d0769ccde89c35da961d6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
* Move board specific SPI registers to devicetree
* Remove unused headers
* Remove obsolete methods
* Fix coding style
* Fix Thinkpad L520 SPI lvscc register
Except for Thinkpad L520, no functional change has been done,
just moving stuff around.
Change-Id: I692a5632030fe2fedbe9a90f86251000f1360fb2
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Do not lock ETR3 CF9GR in early romstage.
As of Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678 this is done
in bd82x6x's finalize handler.
Change-Id: Iea091511f0d2a6128d3a19e9413090c85e4c2e57
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
The AFC—Additional Flash Control Register is set by
southbridge code.
Remove redundant calls and get rid of it in autoport.
Change-Id: I627082e09dd055e3b3c4dd8e0b90965a9fcb4342
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19493
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
TPM ACPI entries are automatically generated, and the old static
TPM ASL file is obsolete. Remove the reference to this obsolete
static and empty ASL file.
Delete src/drivers/pc80/tpm/acpi/tpm.asl.
Change-Id: I6163e6d59c53117ecbbbb0a6838101abb468de36
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19291
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
In the single GPU configuration, the T420 has an LVDS port, one DP++
and one VGA port connected to the IGD. Docking solutions feature up to
two additional DP/DVI-D ports, also directly connected to the IGD.
This makes the list of ports to probe pretty long (takes about 70ms
if nothing but LVDS is connected). We could save about 20~30ms if we'd
limit the ports in case we are not docked or have a discrete GPU.
Change-Id: I8e02c8003ff745d05ee272c59377174847f5219c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19378
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Currently, the USB ports are still powered during S3, so turning
them off may reduce the power consumption.
Note that, when the USB Always on feature is enabled, the USB
ports are always powered, regardless of the USBP state.
This patch also disables the audio, as it might consume some
power or generate some noise.
Both the USB power and the audio are reenabled by coreboot during
the poweron.
Change-Id: If0431b1315fffef2e372e7023f830a66bb7fddae
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18464
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
|
|
This timeout is probably needed on all devices with Lenovo H8 embedded
controllers so set the default there.
Change-Id: I830ab1894f7c0f10f55c82e398becf44d810852d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18274
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
|
|
When MRC cache is available, first read only the SPD unique
identifier bytes required to detect possible DIMM replacement.
As this is 11 vs 256 bytes with slow SMBus operations, we save
about 70ms for every installed DIMM on normal boot path.
In the DIMM replacement case this adds some 10ms per installed DIMM
as some SPD gets read twice, but we are on slow RAM training boot path
anyways.
Change-Id: I294a56e7b7562c3dea322c644b21a15abb033870
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17491
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
The h8s needs around 3s to respond to ps2 commands
Change-Id: I0cf01969975b8dd3839eadf90cb2dac0f1eaafc4
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/16505
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector
code) the reboot counter stored in `reboot_bits` isn't reset on a reboot
with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR
enabled, later stages (e.g. payload, OS) have to clear the counter too,
when they want to switch to normal boot. So change the bits to (h)ex
instead of (r)eserved.
To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also
remove all occurences of the obsolete `last_boot` bit that have sneaked
in again since 24391321 (mainboard: Remove last_boot NVRAM option).
Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/16157
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: I7930d5cded290f2605d0c92a9c465a3f0c1291a2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15974
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Set max_mem_clock_mhz in devicetree to 933Mhz.
Allows to run the memory at up to DDR3-1866.
The same frequency was allowed within the first vendor bios,
but Lenovo than decided to limit it to DDR3-1333.
Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).
The RAM is now running at DDR3-1600 instead of DDR3-1333.
This gives about 4% performance increase in glmark2 using the
Intel GPU.
Change-Id: If15be497402d84a2778f0434b6381a64eda832d6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15158
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Instead of hardcoding the PCI mmio size read it from devicetree.
Set a default value of 2048 MiB and 1024MiB for laptops without
discrete graphics.
Tested on Sandybridge Lenovo T520.
Change-Id: I791ebd6897c5ba4e2e18bd307d320568b1378a13
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15140
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The eSATA port of Lenovo T420 is port 3. I've checked it on an iGPU
model and a dGPU model.
Change-Id: I64bcc887140c1634dd1475d29e97780a5128d0be
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/14632
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
|
|
Enable the PEG device in devicetree to expose the
device if any. This is already default behaviour
for T5xx series.
Change-Id: I16bd253ca96c4cdaad8a829f6490cec9e2599b5f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14448
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
|
|
Add a universal hybrid graphics driver compatible with
all supported lenovo devices.
Hybrid graphics allows to connect the display panel to
either of one GPUs.
As there are only two GPUs one GPIO needs to be toggled.
In case the discrete GPU is activated the panel is routed to it.
On deactivation the panel is routed to the integrated
GPU.
On lenovo laptops the dGPU is always connected to PEG10 and it is
save to disable the PEG slot on dGPU deactivation.
Use common gpio.c for southbridge I82801IX.
Tested on Lenovo T520 using Nvidia NVS 5200m.
Removed Lenovo T430s from the list of supported devices,
as the T430s only supports "muxless Optimus".
Depends on change id:
Iccc6d254bafb927b6470704cec7c9dd7528e2c68
Ibb54c03fd83a529d1ceccfb2c33190e7d42224d8
I8bd981c4696c174152cf41caefa6c083650d283a
Iaf0c2f941f2625a5547f9cba79da1b173da6f295
I994114734fa931926c34ed04305cddfbeb429b62
Change-Id: I9b80b31a7749bdf893ed3b772a6505c9f29a56d1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/12896
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
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Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.
Also, fix up the following driver subdirectories by switching
to the src/drivers/[X]/[Y]/ scheme as these are hard requirements
for the main change:
* drivers/intel
* drivers/pc80
* drivers/dec
Change-Id: I455d3089a317181d5b99bf658df759ec728a5f6b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14047
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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This is based on t420s. Tested on a T420 without discrete GPU.
There is no support for nvidia gpu and optimus.
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: Iru Cai <mytbk920423@gmail.com>
Change-Id: Ie9405966e56180ac1c43a3c5b83181ee500177c8
Reviewed-on: https://review.coreboot.org/11765
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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