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path: root/src/mainboard/lenovo/t400
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2016-08-17mainboard: Clean up boot_option/reboot_bits in cmos.layoutNico Huber
Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector code) the reboot counter stored in `reboot_bits` isn't reset on a reboot with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR enabled, later stages (e.g. payload, OS) have to clear the counter too, when they want to switch to normal boot. So change the bits to (h)ex instead of (r)eserved. To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also remove all occurences of the obsolete `last_boot` bit that have sneaked in again since 24391321 (mainboard: Remove last_boot NVRAM option). Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/16157 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-14src/mainboard: Capitalize ROM, RAM, CPU and APICElyes HAOUAS
Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15987 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-01Add newlines at the end of all coreboot filesMartin Roth
Change-Id: I7930d5cded290f2605d0c92a9c465a3f0c1291a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15974 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31Remove extra newlines from the end of all coreboot files.Martin Roth
This removes the newlines from all files found by the new int-015-final-newlines script. Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15975 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-26intel/gm45: Use common ACPI S3 recoveryKyösti Mälkki
Change-Id: I3148dbbcb06676f48b6bc357124403b70b9bcb6a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15246 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-06-21intel/model_6ex: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
Change-Id: I9bfaa53f8d09962d36df1e86a0edcf100bb08403 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15229 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-17Move definitions of HIGH_MEMORY_SAVEKyösti Mälkki
This is more of ACPI S3 resume and x86 definition than CBMEM. Change-Id: Iffbfb2e30ab5ea0b736e5626f51c86c7452f3129 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15190 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-06-12nb/intel/raminit (native): Read PCI mmio size from devicetreePatrick Rudolph
Instead of hardcoding the PCI mmio size read it from devicetree. Set a default value of 2048 MiB and 1024MiB for laptops without discrete graphics. Tested on Sandybridge Lenovo T520. Change-Id: I791ebd6897c5ba4e2e18bd307d320568b1378a13 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15140 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-04gm45: enable setting all vram sizes from cmosArthur Heymans
Setting the size of the preallocated memory for the igd is done using a cmos parameter, gfx_uma_size. This was limited to a subset of all available sizes, that were already implemented elsewhere in the northbridge code. What this does is change the cmos parameter to 4 bits instead of 3 bits to accomodate all vram sizes. It also adds a sane default of 32mb that already was in place. The northbridge code that reads this cmos parameter is also changed for this new cmos settings. 352M is disabled since it causes issues on systems with 4GB or more ram. TEST: Build, flash target. Clear cmos by corrupting the checksum (nvramtool -c something). Set a desired value in gfx_uma_size using nvramtool. "dmesg | grep stolen" to see what is actually allocated. Change-Id: Ia6479d03f1abe6d0c94bd7264365505e8f8eaeec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/14900 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-06-01mb/lenovo/T4xx: enable PEG devicePatrick Rudolph
Enable the PEG device in devicetree to expose the device if any. This is already default behaviour for T5xx series. Change-Id: I16bd253ca96c4cdaad8a829f6490cec9e2599b5f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14448 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-06-01drivers/lenovo: Add hybrid graphics driverPatrick Rudolph
Add a universal hybrid graphics driver compatible with all supported lenovo devices. Hybrid graphics allows to connect the display panel to either of one GPUs. As there are only two GPUs one GPIO needs to be toggled. In case the discrete GPU is activated the panel is routed to it. On deactivation the panel is routed to the integrated GPU. On lenovo laptops the dGPU is always connected to PEG10 and it is save to disable the PEG slot on dGPU deactivation. Use common gpio.c for southbridge I82801IX. Tested on Lenovo T520 using Nvidia NVS 5200m. Removed Lenovo T430s from the list of supported devices, as the T430s only supports "muxless Optimus". Depends on change id: Iccc6d254bafb927b6470704cec7c9dd7528e2c68 Ibb54c03fd83a529d1ceccfb2c33190e7d42224d8 I8bd981c4696c174152cf41caefa6c083650d283a Iaf0c2f941f2625a5547f9cba79da1b173da6f295 I994114734fa931926c34ed04305cddfbeb429b62 Change-Id: I9b80b31a7749bdf893ed3b772a6505c9f29a56d1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/12896 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-06-01Revert "mainboard/lenovo/t400: Add initial hybrid graphics support"Patrick Rudolph
This reverts commit 59597ead1f26d4c18997bda81b2ec33e52973b80. Will be replaced by lenovo common hybrid driver. Change-Id: I994114734fa931926c34ed04305cddfbeb429b62 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/12895 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-03-15lenovo: add config ONBOARD_VGA_IS_PRIMARYPatrick Rudolph
Fix for the T4xx and T5xx series. It does not apply to X2xx/X6x series as those have only one GPU, which is always connected to the display. The T6x series needs special care not handled with this patch. Without ONBOARD_VGA_IS_PRIMARY the onboard GPU would be deactivated in case a dedicated GPU is found and active, leaving the system without a working display. Change-Id: I94d1700e9afb75de83a4f2ed1ff53ba3b0559ae1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14031 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2016-02-09Workaround for unused variable warning.Vladimir Serbinenko
Change-Id: I0a0c925509027f98f724d0a4347146f21ac06c02 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13624 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19lenovo/t400: Revise onboard IRQ routingNico Huber
All southbridge interrupt pin and routing registers (D*IP and D*IR) are left at their default values (see ICH9 datasheet) and this file just has to reflect them. Change-Id: I1e9732e178bb8422b284d80d9f3d34b72f2e2415 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/13040 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-14mainboard/lenovo: reserve century byteAlexander Couzens
The century byte is used by most RTC (default 0x32@nvram). Even the century byte can disabled via ACPI it's more safe to reserve it's space. Because some RTC will act with that byte anyhow. Some OS overwrite it when syncronize the RTC. Change-Id: I078c0c57215ccb925afa85b9d067f15268801ec9 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/11853 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-12-08lenovo/t500: Add clone of Lenovo T400Francis Rowe
The existing code for the Lenovo T400 works without changes on the Lenovo T500. Same HDA verbs are provided by Lenovo BIOS on both laptops. Change-Id: I300408a8a0ed00476aee6061925befc2822fb505 Signed-off-by: Francis Rowe <info@gluglug.org.uk> Reviewed-on: https://review.coreboot.org/10545 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-24lenovo t400: Fix IASL warning and remarkMartin Roth
If any path in a method returns a value, IASL expects that all paths within that method will return a value. Presumably, the ATPX would not need a return value if Arg0 is anything other than 0, so just return a zero. - Serialize ATPX method to make IASL happy. This means that it can only be used by one thread at a time. Fixes these issues: dsdt.aml 2581: Method (ATPX, 2, NotSerialized) { Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) dsdt.aml 2581: Method (ATPX, 2, NotSerialized) { Warning 3115 - ^ Not all control paths return a value (ATPX) Change-Id: I14aeab0cebe4596e06a17cffc36cc01b953d7191 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12518 Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-23IASL: Enable warnings as errorsMartin Roth
We've actually got more warnings now than when I first tested IASL warnings as errors. Because of this, I'm adding it with the option to have it disabled, in hopes that things won't get any worse as we work on fixing the IASL warnings that are currently in the codebase. - Enable IASL warnings as errors - Disable warnings as errors in mainboards that currently have warnings. - Print a really obnoxious message on those platforms when they build. ***** WARNING: IASL warnings as errors is disabled! ***** ***** Please fix the ASL for this platform. ***** Change-Id: If0da0ac709bd8c0e8e2dbd3a498fe6ecb5500a81 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10663 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-19lenovo/r400: Add clone of Lenovo T400Michał Masłowski
The existing code for the Lenovo T400 works without changes on the Lenovo R400. Same HDA verbs are provided by Lenovo BIOS on both laptops. Change-Id: I1dadddd7250ab80a4c40c2435865d72e3e5d99c9 Signed-off-by: Michał Masłowski <mtjm@mtjm.eu> Signed-off-by: Francis Rowe <info@gluglug.org.uk> Reviewed-on: http://review.coreboot.org/8393 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-11-10mainboard/lenovo/t400: Add initial hybrid graphics supportTimothy Pearson
TEST: Booted T400 with Intel/ATI hybrid graphics in integrated mode with native Intel graphics init and verified integrated panel framebuffer functionality in SeaBIOS and Linux. Change-Id: I37e72c5dad0d7ab3915cc3d439ae9a4a9b3787e3 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9319 Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2015-11-05mainboard: Remove last_boot NVRAM optionTimothy Pearson
The last_boot NVRAM option was deprecated and removed in commit 3bfd7cc6. Remove the last_boot option from all affected mainboards to eliminate user confusion. Change-Id: I7e201b9cf21dfe5dda156785bad078524098626d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12316 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-23lenovo/t400: Consolidate `acpi/platform.asl`Paul Menzel
The ASL code is already present in `southbridge/intel/common/acpi/platform.asl` and `cpu/intel/common/acpi/cpu.asl`. So include these files instead of duplicating the code. Something similar was don in commit commit 24813c14 (i945: Consolidate acpi/platform.asl). Change-Id: Ide50b34184b80c86b996f86dd589c3cf3bf75587 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11883 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-22gma ACPI: Make brightness levels a per board settingNico Huber
Those are actually board specific. Keep the old value as defaults, though. The defaults are included by all affected boards. Change-Id: Ib865c7b4274f2ea3181a89fc52701b740f9bab7d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/11705 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-10-11Kill lvds_num_lanesVladimir Serbinenko
Only one value would work with corresponding gma code currently (which one depends on board). Going forward, it's possible to compute which number can be used, so there is no need to keep this info around. Change-Id: Iadc77ef94b02f892860e3ae8d70a0a792758565d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/11862 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-10-11Derive lvds_dual_channel from EDID timings.Vladimir Serbinenko
Based on the info by Felix Held. Change-Id: Iab84dd8a0e3c942da20a6e21db5510e4ad16cadd Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/11857 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-06-24Remove address from GPLv2 headersPatrick Georgi
Follow up for commit b890a12, some contributions brought back a number of FSF addresses, so get rid of them again. Change-Id: Icf83d5e2a3daea385af3572e9eac6b2431652c28 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10640 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-14mainboard/lenovo/t400: Fix HDA verbs to match hardware layoutMichał Masłowski
The same values are used on my Lenovo R400 as reported by Francis Rowe from his T400 and T500. TEST: Read /proc/asound/card0/codec#0, see that the jack locations correspond to the board layout, e.g. headphone and microphone connectors are on front of the laptop, not right. Read /sys/class/sound/hwC0D0/init_pin_configs, see that it has the same content as with factory firmware. Change-Id: I60e914ca9fab4bb2c99b4ed9e6d81a0580a88b18 Signed-off-by: Michał Masłowski <mtjm@mtjm.eu> Reviewed-on: http://review.coreboot.org/10431 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-06-10mainboard/lenovo/t400: Add initial ATPX ACPI implementationTimothy Pearson
Change-Id: I9b86ebec59ccb63db0e1ba61533d162507a22379 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9320 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-06-10lenovo/t400: Fix buildKyösti Mälkki
Change-Id: I8e8b6e7c123e641749c42a7c706176e285902bb5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10502 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-06-10mainboards/lenovo/t400: Remove X200-specific codeTimothy Pearson
Change-Id: Ic3503938b996bbf31f1417923f019a7bc722b9fd Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/10429 Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: build bot (Jenkins)
2015-06-10mainboards/lenovo: Copy X200 board to T400 for future expansionTimothy Pearson
Change-Id: If2d48b84fe7bd7b144e96171e54067891e3c4e2e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9316 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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