coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2024-08-28	tree: Use boolean for "eist_enable"	Elyes Haouas
	Change-Id: I4fc824bef1daf8c12eb671c58de9019ce5a23a2e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2024-06-23	skl mainboards: Move cpu_cluster device to chipset devicetree	Felix Singer
	Change-Id: I7114612e686a0bf3cfc241f45fa62077fad16f5a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-07	mb/**/hda_verb: Use `AZALIA_PIN_CFG_NC(0)`	Angel Pons
	Replace `0x411111f0` with `AZALIA_PIN_CFG_NC(0)`, which evaluates to the same value and conveys additional information to the reader. Done with a bulk search and replace operation. Change-Id: Ibd84daec017bc1ab1ee4edd906fda80231c134cc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-30	tree: Remove duplicated <soc/gpio.h>	Elyes Haouas
	<gpio.h> is supposed to chain-include <soc/gpio.h>. Change-Id: Ib25581bd2c8dd38cdd0396561ce5f9a782365f14 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82691 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-26	mb/lenovo: Remove blank lines before '}' and after '{'	Elyes Haouas
	Change-Id: I6ece868184dd772fc2c3c472ae2172d1c34fb179 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81484 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-29	mb/lenovo: Add ThinkCentre M700/M900 Tiny board (Skylake/Kaby Lake)	Michał Kopeć
	The M700 / M900 Tiny boards are USFF PCs that come with Skylake LGA1151 processors. M700 comes with B150 chipset, M900 comes with Q170 and is vPro capable. There is an onboard discrete TPM 1.2. Intel PTT fTPM can also be enabled in vendor FW, but for now it's not used here. LPSS UART for debugging is available on pins 17,18 on the underside of the mainboard, but it is not enabled by default. Tested unit is M900 with i5-6500T. Boots to Fedora 38 w/ kernel 6.5.5 and Windows 11. Tested and working: - Serial port (via optional module) - Rear DisplayPort connectors - Graphics w/ libgfxinit - Ethernet - SATA - NVMe - Internal speaker, front combo jack, rear line-out - Discrete TPM 1.2 - USB ports (Port 1 untested, apparently broken on my unit) - M.2 2230 Wi-Fi slot (needs ASPM L1s disabled) - S3 suspend - ME disable via NVRAM setting Untested: - Front mic input - Optional expansion headers: DisplayPort, USB, PS/2, SATA / PCIe Change-Id: I6786e068ec03c8bf243e1767cd7b9d50512ea77f Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>