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2015-05-28igd.asl rewriteVladimir Serbinenko
Old igd.asl had inconsistent addresses (between _DOD and actual device) and ghost devices. Any of those is enough to make brightness on windows fail and make igd.asl out-of-ACPI-spec. Also old code favoured ridiculous copying of the same thing 6 times per chipset. Leave only hooking up and chipset-specific part in chipset directory. Move NVS handling and ACPI-spec parts to a common file. Change-Id: I556769e5e28b83e7465e3db689e26c8c0ab44757 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7472 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-05-26speedstep: Don't supply weak get_cst_entries.Vladimir Serbinenko
This should be overriden by mobo even if it's no-op override. weak function in this case would only hide real problems. Change-Id: I30dd671eb605b490a51153d00ae308c4bdef3d05 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7368 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-20acpi: make fill_slit and fill_srat into arguments.Vladimir Serbinenko
SLIT and SRAT are created this way only on amdk8 and amdfam10. This saves the need of having a lot of dummies. Change-Id: I76d042702209cd6d11ee78ac22cf9fe9d30d0ca5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7052 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-19Move smi trap sample to documentation, don't keep it in every mobo.Vladimir Serbinenko
Sample code belongs to documentation, not copied 100x over prodcution code. Change-Id: I6bb318d76057d02bd6ac5641d12d56ab6d60b745 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10229 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-22kontron/986lcd-m: update vendor URLPatrick Georgi
Change-Id: Ia43291d0d41e565f2442b625387f3ffde9a98d32 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/9947 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-22kontron/986lcd-m: Add release yearPatrick Georgi
Change-Id: Ie49e235b81ca0cd7aff05ceed522d9df1d5403b0 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/9946 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-18kconfig: automatically include mainboardsStefan Reinauer
This change switches all mainboard vendors and mainboards to be autoincluded by Kconfig, rather than having to be mentioned explicitly. This means, vendor and mainboard directories are becoming more "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree mainboards / components to be built with a given coreboot version (given that the API did not change) Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: Ib68ce1478a2e12562aeac6297128a21eb174d58a Reviewed-on: http://review.coreboot.org/9295 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-06global: Refactor get_option usageVarad Gautam
Restructure get_option() calls to avoid unnecessary return value checks by pre-assigning defaults to the options being retrieved. Change-Id: I9159afe149a8eeed0785d1efd6eee8420b88b8f4 Signed-off-by: Varad Gautam <varadgautam@gmail.com> Reviewed-on: http://review.coreboot.org/8631 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-16acpi: Generate valid ACPI processor objectsTimothy Pearson
The existing code generated invalid ACPI processor objects if the core number was greater than 9. The first invalid object instance was autocorrected by Linux, but subsequent instances conflicted with each other, leading to a failure to boot if more than 10 CPU cores were installed. The modified code will function with up to 99 cores. Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8422 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-16mainboard/cmos: Delete obsolete commented parametersTimothy Pearson
Change-Id: Iccad79c142a7fcf89dd0fbebe8c07ad9ef019e91 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8459 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
2015-01-06mainboard/*/romstage.c: Sanitize system header inclusionsEdward O'Callaghan
Fix system include paths to be consistent. Chipset support is part of the Coreboot 'system' and hence 'non-local' (i.e., in the same directory or context). One possible product of this, is to perhaps allow future work to do pre-compiled headers (PCH) on the buildbot for faster build times. However, this currently just makes mainboard's consistent. Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8085 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-06kontron/986lcd-m: Fix PCI interrupt routing.Vladimir Serbinenko
The current interrupt routing shares interrupt 5 between LPC and PCI which isn't possible. Use IRQ 11 for all devices in PCI mode. Move conflicting LPC to free IRQ. Change-Id: I3ac8c2f19195ef6b07f4ee7dde64dd038d024126 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7477 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-03i945: Consolidate acpi/platform.aslVladimir Serbinenko
Change-Id: Iccb2dda8a427e483c04693e46b00e0bc2452a26b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7086 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-03i82801gx: Enable upper CMOS in bootblock.Vladimir Serbinenko
Otherwise checksum may not work correctly on early stages. For compatibility with old bootblocks also enable it early in romstage. Change-Id: Ie541d71bd76af182e445aa5ef21fe5ba77091159 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7556 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-02Replace hlt with halt()Patrick Georgi
There were instances of unneeded arch/hlt.h includes, various hlt() calls that weren't supposed to exit (but might have) and various forms of endless loops around hlt() calls. All these are sorted out now: unnecessary includes are dropped, hlt() is uniformly replaced with halt() (except in assembly, obviously). Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7608 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-09i945: consolidate sb & nb early initsVladimir Serbinenko
Change-Id: I00c2c725de5b982a5e4f584b77b09017a5bc0a72 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7062 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-11-09i945: Consolidate common GNVS initVladimir Serbinenko
Change-Id: Idc3522807b17e56bdaf8f04b4bd68c6ed9777363 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7110 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-04i82801gx: Handle whole FADT in southbridge.Vladimir Serbinenko
Do all the handling in SB code with few parameters from devicetree.cb instead of having mobo callbacks. Change-Id: I8fd02ff05553a3c51ea5f6ae66b8f5502509e2bc Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7199 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-18i945: Consolidate FADT codeVladimir Serbinenko
Change-Id: I076cba7d21926cabf90d485de50268ae40c435f3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7087 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-15i945: Convert to per-device ACPIVladimir Serbinenko
Change-Id: Iee3ee33ca58b8c722d2d38aae31e7130032512ad Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6804 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-13azalia: Shrink boilerplateVladimir Serbinenko
Change-Id: Ib3e09644c0ee71aacb067adaa85653d151b52078 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6840 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-05Consolidate intel vga int15 hooksVladimir Serbinenko
Change-Id: I9366dded98bf15f6da44ce893dd10698ba09fd55 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6820 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18azalia: Move shared variable to separate fileVladimir Serbinenko
Change-Id: Icf46ad1397c67478887c80a627b8f4eb0a67e542 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6695 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-15intel/cpu: rename car.h to romstage.hAaron Durbin
This header has nothing to do with cache-as-ram. Therefore, 'car' is the wrong term to use. It is about providing a prototype for *romstage*. Change-Id: Ibc5bc6f3c38e74d6337c12f246846853ceae4743 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/6661 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-14Intel: Add common header file for CAR setupEdward O'Callaghan
When passing '-ffreestanding' the 'main' romstage.c may no longer necessarily be considered the entry point. From the C specification in 5.1.2.1 Freestanding environment; "In a freestanding environment (in which C program execution may take place without any benefit of an operating system), the name and type of the function called at program startup are implementation-defined." Clang complains about these being missing as Clang is somewhat more strict about the spec than GNU/GCC is. An advantage here is that a different entry-point type-signature shall now be warned about at compile time. Change-Id: I467001adabd47958c30c9a15e3248e42ed1151f3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5872 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-18mainboard: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: If29a70be4fb56ebb0dbf6d510412cbe2f34480ef Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6291 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-07-17mainboard,ASL: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: Ib531a54db7df6b49a6218f689dcaab712e9dfb01 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6292 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-08mainboard: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I05d6d22664155ac8478e665733f816776e277c22 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6200 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-25i945 boards: Switch to use DYNAMIC_CBMEMKyösti Mälkki
Change-Id: I1bbcba086f841a90544b827ae807a3c351d19d21 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6036 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-25i945 boards: Drop disabled ram_check() callsKyösti Mälkki
This code would not get enabled just by flipping the options in menuconfig, also ramcheck() no longer test the range like the parameters would imply. We should add non-destructive ram_check() on S3 resume path to verify memory controller configuration has been properly recovered. Change-Id: Ie4675c4770146c4312cdfbc81afa19f243f90ee4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6027 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-20intel/i945 gm45: Use acpi_s3_resume_allowed()Kyösti Mälkki
Change-Id: I7811ee695f35c708144c4af5d43935deb22dd4df Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6061 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-28superio/winbond/w83627thg: Depreciate romstage componentEdward O'Callaghan
Depreciate the model specific early_serial.c romstage component for this Super I/O in favor of the recent generic winbond romstage framework. Change-Id: I22775dc9b6341c8994d21591b7176abe4dd99911 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5724 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-20drivers: Drop GbE stub driversEdward O'Callaghan
These NIC stub drivers were to initialize the Gigabit Ethernet adapters just enough to keep coreboot from trying to execute an option ROM. However this is no longer required as non-VGA option roms are not ran; See: b32816e Remove PCI_ROM_RUN option Change-Id: Idc44619767c631c5fcf550a5948c8947bde5e218 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5777 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-19intel: Remove GFXUMA and related global variablesKyösti Mälkki
Remove use of global variables uma_memory_base and uma_memory_size from builds with Intel northbridges, as these variables can be kept within the chipset or even as stack locals. Intel platforms have no functional implemenation for option GFXUMA. If we did implement some choice between external and integrated graphics, it needs to be named in less obscure fashion. Change-Id: I12f18c4ee6bc89e65a561db6c2b514956f3e2d03 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5720 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-03Move ARCH_* from board/Kconfig to cpu or soc Kconfig.Furquan Shaikh
CONFIG_ARCH is a property of the cpu or soc rather than a property of the board. Hence, move ARCH_* from every single board to respective cpu or soc Kconfigs. Also update abuild to ignore ARCH_ from mainboards. Change-Id: I6ec1206de5a20601c32d001a384a47f46e6ce479 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5570 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-29mainboard/kontron/986lcd-m: Remove a duplicate headerEdward O'Callaghan
Change-Id: I0dd50722c1ccbcb8a21b8fbab4d706d6b2f2b130 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5602 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-06superio/winbond/w83627thg: Avoid .c includesEdward O'Callaghan
Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: I1f7c20ac7841874125b6bfcd9f9db25d96355881 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5449 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-22CBMEM: Replace cbmem_initialize() with cbmem_recovery()Kyösti Mälkki
The replacement function confirms CBMEM TOC is wiped clean on power cycles and resets. It also introduces compatibility interface to ease up transition to DYNAMIC_CBMEM. Change-Id: Ic5445c5bff4aff22a43821f3064f2df458b9f250 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4668 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-01-22intel/i945 boards: Add EARLY_CBMEM_INITKyösti Mälkki
Inspired by commits ac6ea04b and 4560ca50 that enabled this feature for lenovo/x60 and lenovo/t60 with i945 chipset. Change-Id: Ia04f58b8c3769b5734708c6a338bb80c13c5aeba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3994 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-01-19board-status: Add board_info.txt extracted from wiki.Vladimir Serbinenko
board_info.txt is a file to be used by board-status to add some useful info to the generated table like flash chip type. This series is autogenerated from wiki page Supported_Motherboards. Change-Id: Ie2bda900713ef4883134477163320936c84c34f5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4701 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-24Remove PCI_ROM_RUN optionVladimir Serbinenko
The main purpose of option rom is to supply int* handlers. But supplying those is outside of coreboot scope and if someone needs those they should run SeaBIOS anyway which runs the option roms wonderfully. Running VGA oprom is kept because they're needed to init graphics. This patch still keeps the options to include the option roms to make them available to SeaBIOS. Change-Id: I646334cf88094d3bf8f527779a68a07e0b4b93ec Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4545 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
2013-12-02global: Fix usage of get_option() to make use of CB_CMOS_ codesAlexandru Gagniuc
Do not directly check the return value of get_option, but instead compare the returned value against a CB_CMOS_ error code, or against CB_SUCCESS. Change-Id: I2fa7761d13ebb5e9b4606076991a43f18ae370ad Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4266 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-25Unify and clean up remaining INT15 handlersStefan Reinauer
Some handlers still had 2 variants, others were incorrectly guarded by CONFIG_ variables. This patch straightens them out. This does not touch the siemens/sitemp_g1p1 which provides an interestingly complex solution for the int15 handler. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I5d74fdf7c2ab1faa96ebc2b5ca5c69398449b069 Reviewed-on: https://gerrit.chromium.org/gerrit/48979 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Commit-Queue: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4140 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-11CBMEM: Drop parameter from cbmem_reinit()Kyösti Mälkki
Function is always called with get_top_of_ram() - HIGH_MEMORY_SIZE which equals cbmem_base, thus no need to pass it as a parameter. Change-Id: If026cb567ff534716cd9200cdffa08b21ac0c162 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3564 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-07-04intel/i945: Use MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Change all PCI configuration accesses to MMIO on all boards with i945 chipset. To enable MMIO style access, add explicit PCI IO config write in the bootblock. Change-Id: Ia1ab73f1a2dcda87db4eb9b2ffddc6f7b4382b01 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3584 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-03-22x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer
Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14sconfig: rename lapic_cluster -> cpu_clusterStefan Reinauer
The name lapic_cluster is a bit misleading, since the construct is not local APIC specific by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-x86 systems without adding new keywords. Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2377 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14sconfig: rename pci_domain -> domainStefan Reinauer
The name pci_domain was a bit misleading, since the construct is only PCI specific in a particular (northbridge/cpu) implementation, but not by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-PCI systems without adding new keywords. Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2376 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-04Intel based boards: Use tab instead of spaces to align comment in DSDTPaul Menzel
Mainboards using `COREBOOT` as their OEM Table ID in their DSDT header were copied from the same source and therefore had spaces instead of a tab to align that comment for that header field. These are mostly Intel based boards. Fix that in accordance with the coding style [1]. [1] http://www.coreboot.org/Development_Guidelines#Coding_Style Change-Id: I299b955930dbd50b9717e8ff141ce8f3fd534e5f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2277 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-01-03Rename mainboard_smi.c to smihandler.cPatrick Georgi
This mirrors the naming convention of handlers in northbridge and southbridge. Change-Id: I45d97c569991c955f0ae54ce909d8c267e9a5173 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2058 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24Remove duplicate VGA BIOS interrupt handlersPatrick Georgi
Some boards have two instances of the int15 handler that supports the onboard VGA BIOS, for YABEL and realmode. These are now similar enough that they can be deduplicated. Due to minor differences this requires manual effort. Change-Id: I03ae314cb90dd65d96591ce448504aa961cbeb88 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1893 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24yabel: Use X86_* instead of the more verbose M.x86.REG_*Patrick Georgi
Makes it more similar to what realmode looks like. Change-Id: I4407431f2d979c43dd186114d67ed11845907afe Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1892 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24x86 realmode: Use x86emu register file + definesPatrick Georgi
By using the (global) register file as defined by x86emu, we can use the same register access for YABEL and realmode interrupt handlers. - the x86 realmode interrupt handlers changed in signature - to access registers, use X86_$REGNAME now (eg. X86_EAX) - x86_exception_handler still uses struct eregs *regs to avoid spilling the x86emu register file stuff everywhere Coccinelle script that handled most of this commit: @ inthandler @ identifier FUNC, regs; @@ int FUNC( -struct eregs *regs +void ) { ... } @ depends on inthandler @ identifier regs; @@ -regs->eax +X86_EAX @ depends on inthandler @ identifier regs; @@ -regs->ebx +X86_EBX @ depends on inthandler @ identifier regs; @@ -regs->ecx +X86_ECX @ depends on inthandler @ identifier regs; @@ -regs->edx +X86_EDX @ depends on inthandler @ identifier regs; @@ -regs->esi +X86_ESI @ depends on inthandler @ identifier regs; @@ -regs->edi +X86_EDI @ depends on inthandler @ identifier regs; @@ -regs->eflags +X86_EFLAGS @ depends on inthandler @ identifier regs; @@ -regs->vector +M.x86.intno Change-Id: I60cc2c36646fe4b7f97457b1e297e3df086daa36 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1891 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24x86 realmode: Adapt to x86emu/YABEL style return codesPatrick Georgi
realmode int handlers must return the same codes as the YABEL int handlers now: 1 for "interrupt handled", 0 for "not handled" (ie. error). Change-Id: Idc01cf64e2c97150fc4643671a0bc4cca2ae6668 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1890 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-16Fix PIRQ routing abstractionStefan Reinauer
intel_irq_routing_table is a local structure that should not be used globally, because it might not be there on all mainboards. Instead, the API has to be corrected to allow passing a PIRQ table in where needed. Change-Id: Icf08928b67727a366639b648bf6aac8e1a87e765 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1862 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-16Drop unneeded BOARD_HAS_FADT optionStefan Reinauer
Change-Id: Iaaeee87d70cf052bc7980007cdf1f7dda88b3623 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-16Reduce number of per-mainboard changesStefan Reinauer
- Add mainboard_smi.c from arch/x86/Makefile if it's there - Add mainboard's chromeos.c from the chromeos Makefile Change-Id: I3f80e2cb368f88d2a38036895a19f3576dd9553b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1835 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14Move HAVE_SMI_HANDLER from mainboards to chipsetsStefan Reinauer
Change-Id: Ibb6606fe3996e377181872a4544600f2d58c5439 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1834 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-06Drop redundant CHIP_NAME in mainboard.cKyösti Mälkki
Compose the name from Kconfig strings instead. As the field is for debug print use only, a minor change in the output should do no harm. The strings no longer include word "Mainboard". Change-Id: Ifd24f408271eb5a5d1a08a317512ef00cb537ee2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1635 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-08hpet: common ACPI generationPatrick Georgi
HPET's min ticks (minimum time between events to avoid losing interrupts) is chipset specific, so move it to Kconfig. Via also has a special base address, so move it as well. Apart from these (and the base address was already #defined), the table is very uniform. Change-Id: I848a2e2b0b16021c7ee5ba99097fa6a5886c3286 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1562 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2012-10-05Use mainboard_interrupt_handlers everywherePatrick Georgi
The previous commit provides a mainboard_interrupt_handlers implementation YABEL with identical semantics to the x86emu one, so let's use it in both cases. This eliminates the need for the int15_install() indirection, so let's drop that, too. Generated using the following coccinelle patch and manual cleanups (empty #if/#endif): @@ type T; identifier FUNCARR; expression INT, HANDLER; @@ -typedef T yabel_handleIntFunc; -extern yabel_handleIntFunc FUNCARR[256]; -FUNCARR[INT] = HANDLER; +mainboard_interrupt_handlers(INT, &HANDLER); @@ @@ -void int15_install(void) -{ -mainboard_interrupt_handlers(0x15, &int15_handler); -} @@ @@ -void int15_install(void) -{ -mainboard_interrupt_handlers(0x15, &int15_handler); ... mainboard_interrupt_handlers(0x15, &int15_handler); -} @@ @@ -int15_install(); +mainboard_interrupt_handlers(0x15, &int15_handler); Change-Id: I70fd780d7ebf1564a2ff7d7148411673f6de113c Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1559 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-26Drop mainboard chip.hStefan Reinauer
mainboard_config never worked right, at least not since we've had sconfig. Hence, drop mainboard/<vendor>/<device>/chip.h and fix up the mainboards that tried to use it anyways. Change-Id: I7cd403ea188d8a9fd4c1ad15479fa88e02ab8e83 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1359 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-26Remove copies of rtl8168.cPatrick Georgi
One copy was slightly different, but all the differences were commented out Change-Id: I3cc7b5621c681a1eb286f9b16ef3ebdce03abb6b Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1356 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-05-01Drop CONFIG_MAX_PHYSICAL_CPUS on non-AMD boardsStefan Reinauer
CONFIG_MAX_PHYSICAL_CPUS is defined by quite a number of mainboards whithout any code actually using the variable. Hence, drop MAX_PHYSICAL_CPUS from Kconfig for those boards. In the long run we should drop CONFIG_MAX_PHYSICAL_CPUS use completely and make the code dynamic or depend on CONFIG_MAX_CPUS instead. Change-Id: I37dcc74d245ddba5186b96bd82220dacb6f4d323 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/984 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-04-20Refactor some alignment handlingPatrick Georgi
Made using coccinelle: @@ expression E; @@ -(E + 7) & -8 +ALIGN(E, 8) @@ expression E; @@ -(E + 15) & -16 +ALIGN(E, 16) Change-Id: I071d2c98cd95580d7de21d256c31b6368a3dc70b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/910 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-16Intel northbridge I945: Apply un-written naming rulesKyösti Mälkki
Use NORTHBRIDGE_INTEL_I945 to select the driver directory for build. Use _SUBTYPE_945GC and _SUBTYPE_945GM to define at compile-time which model of I945 the driver is built for. Change-Id: I11b1e0998d0fc28f8946bad4f0989036a9b18af4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/684 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-08Unify Local APIC address definitionsPatrick Georgi
We used several names for that same value, and hardcoded the value at some more places. They're all LOCAL_APIC_ADDR now (except for lapic specific code that still uses LAPIC_DEFAULT_BASE). Change-Id: I1d4be73b1984f22b7e84681edfadf0588a7589b6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/676 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-22ACPI: More ../../.. removalPatrick Georgi
CPP is ran with src/ as part of its search path, so using <northbridge/...> and the like is safe. Change-Id: I644d60190ac92ef284d5f0b4acf44f7db3c788ee Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/649 Tested-by: build bot (Jenkins)
2012-01-31northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig optionPeter Stuge
Originally brought up by Sven Schnelle in March 2011 http://patchwork.coreboot.org/patch/2801/ http://www.coreboot.org/pipermail/coreboot/2011-March/064277.html On some mainboards it may be neccessary to reset early during resume from S3 if the SLFRCS register indicates that a memory channel is not guaranteed to be in self-refresh. On other mainboards, such as Lenovo X60 and T60, the check always creates false positives, effectively making it impossible to resume. The SLFRCS register is documented on page 197 of Mobile Intel® 945 Express Chipset Family Datasheet Document Number: 309219-006 which is publically available, and the register indicates if a memory channel is guaranteed to be in self-refresh mode (if bit = 1), or that a memory channel *may or may not be* in self-refresh mode (if bit = 0). The register can thus only be used to positively learn that memory is in self-refresh. It is not known for sure that memory is *not* in self-refresh. The register is reset by the PWROK signal, which *should* go low during S3, and go high again when resuming, so it is unsurprising that SLFRCS has already been cleared when we read the register. Sven's measurements of the CKE signal on a ThinkPad shows that memory remains in self-refresh indefinitely, until coreboot re-initializes the memory controller, even when SLFRCS bits were = 0. Boards which require a warm reset when SLFRCS bits are cleared must now explicitly enable the check in the mainboard Kconfig file. This commit selects the new option in all existing i945 mainboards. A follow-up commit will remove the option for ThinkPads. Change-Id: I02320675efb8fde05c371ef243ba5093a4da6d11 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/590 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2011-10-30remove usbdebug.h include from mainboard/romstage codeSven Schnelle
No romstage is supposed to use usbdebug functions/defines directly, so remove all those includes. The usb code is now called and setup from console code. Change-Id: I9b1120d96f5993303d6b302accc86e14a91f7a9f Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/354 Tested-by: build bot (Jenkins)
2011-10-28Get rid of the old romstage-as-bootblock ROM layoutPatrick Georgi
This change removes CONFIG_TINY_BOOTBLOCK, CONFIG_BIG_BOOTBLOCK, and all their uses, assuming TINY_BOOTBLOCK=y, BIG_BOOTBLOCK=n. This might break a couple of boards on runtime, but so far, fixes were quite simple. There's a flag day: Code that relies on CONFIG_TINY_BOOTBLOCK must be adapted. Change-Id: I1e17a4a1b9c9adb8b43ca4db8aed5a6d44d645f5 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/320 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-13Refactor option rom initialization code in coreboot.Stefan Reinauer
- move int15 handler out of the generic code into the mainboard directories of those mainboards that actually use it. - move vbe headers to vbe.h - move function prototypes used in native oprom code to x86.h Change-Id: Idfff5e804ea328f7b5feebac72497c97329320ee Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/255 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13Use default table creator macro for all SSDTsStefan Reinauer
Change-Id: I0c138ebfdc6d4d5ae7d3512b0dd68df20485690e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/262 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13mptable: Refactor mptable generation some morePatrick Georgi
The last couple of lines of every mptable function were mostly identical. Refactor into common code, a new function mptable_finalize. Coccinelle script: @@ identifier mc; @@ ( -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); -printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); -return smp_next_mpe_entry(mc); +return mptable_finalize(mc); | -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); -return smp_next_mpe_entry(mc); +return mptable_finalize(mc); ) Change-Id: Ib2270d800bdd486c5eb49b328544d36bd2298c9e Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/246 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13mptable: Get rid of fixup_virtual_wirePatrick Georgi
As stated in some code files, fixup_virtual_wire was established to avoid touching 200 invocations of the mptable code. Let Coccinelle do it: @@ type T; identifier v; @@ -void fixup_virtual_wire(T v) -{ ... } @@ expression A; identifier v; @@ -v = smp_write_floating_table(A); +v = smp_write_floating_table(A, 0); @@ expression A; identifier v; @@ -v = smp_write_floating_table(A, 0); -fixup_virtual_wire(v); +v = smp_write_floating_table(A, 1); Change-Id: Icad8a063380bf4726be7cebb414d13b574112b14 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/245 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13mptable: Refactor lintsrc generationPatrick Georgi
We copied pretty much the same code for generating mptable entries for local interrupts (with some notable exceptions). This change moves these lines into a generic function "mptable_lintsrc" and makes use of it in many places. The remaining uses of smp_write_lintsrc should be reviewed and replaced by mptable_lintsrc calls where possible, and smp_write_lintsrc made static. This patch was generated using Coccinelle: @@ expression mc; expression isa_bus; @@ -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, isa_bus); @@ expression mc; expression isa_bus; @@ -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0); -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, isa_bus); @m@ identifier mc; expression BUS; @@ -#define IO_LOCAL_INT(type, intr, apicid, pin) smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, BUS, (intr), (apicid), (pin)); ... -IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); -IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, BUS); Change-Id: I97421f820cd039f5fd753cb0da5c1cca68819bb4 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/244 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-21Use ACPI text fields consistently with all other boardsStefan Reinauer
LXBIOS and LXB-DSDT are not used in other parts of the tree. Make names consistent across the tree. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I91caeac09fd2401a36e53bd061d249b236a48e43 Reviewed-on: http://review.coreboot.org/224 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-08-26Add automatic SMBIOS table generationSven Schnelle
Change-Id: I0ae16dda8969638a8f70fe1d2e29e992aef3a834 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/152 Tested-by: build bot (Jenkins)
2011-06-15i82801gx: replace cafed00d/cafebabe by definesSven Schnelle
We're using '0xcafed00d' all over the code as magic for ACPI S3 resume. Let's add a define for that. Also replace 0xcafebabe by a define. Change-Id: I5f5dc09561679d19f98771c4f81830a50202c69f Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/33 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-06-07SMM: add defines for APM_CNT registerSven Schnelle
in the current code, the defines for the APM_CNT (0xb2) register are duplicated in almost every place where it is used. define those values in cpu/x86/smm.h, and only include this file. And while at it, fixup whitespace. Change-Id: Iae712aff53322acd51e89986c2abf4c794e25484 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/4 Tested-by: build bot (Jenkins)
2011-05-10Change read_option() to a macro that wraps some API uglynessPatrick Georgi
Simplify read_option(CMOS_VSTART_foo, CMOS_VLEN_foo, somedefault) to read_option(foo, somedefault) Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6565 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-21some ifdef --> if fixesStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20run uart_init() from console_init, just like the other console ↵Stefan Reinauer
initialization functions. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-18* Set USBDEBUG_DEFAULT_PORT in all southbridges and use that valueStefan Reinauer
to unify calls to *_enable_usbdebug() * rename *_enable_usbdebug() to enable_usbdebug() * move enable_usbdebug() to generic romstage console init code and drop it from the individual romstage.c files. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-21[i945] Add SPD adress mappingSven Schnelle
The current code works only with dual channel if Channel 0 uses SPD address 0x50/0x51, while the second channel has to use 0x52/0x53. For hardware that uses other addresses (like the ThinkPad X60) this means we get only one module running instead of both. This patch adds a second parameter to sdram_initialize, which is an array with 2 * DIMM_SOCKETS members. It should contain the SPD addresses for every single DIMM socket. If NULL is given as the second parameter, the code uses the old addressing scheme. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6374 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-27Add a new CMOS variable which triggers activation of thePatrick Georgi
LPT port. With the CMOS variable set, LPT is found by SeaBIOS, with the variable reset, it's not. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-27oops. this is weird. CAR addresses should be specified in the socket and not inStefan Reinauer
the board. I thought we did this ages ago. Also push CAR BASE further down so it won't conflict with a 32mbit flash part. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-14Allow coreboot to initialize CMOS if checksum is invalid.Patrick Georgi
If a file "cmos.default", type "cmos default"(0xaa) is in CBFS, a wrong checksum leads to coreboot rewriting the first 128 bytes (except for clock data) with the data in cmos.default, then reboots the system so every component of coreboot works with the same set of values. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-13Default to CRT on Kontron/986lcd-m. "default display" doesn't alwaysPatrick Georgi
select the right output device. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-19The same mechanisms are used for normal and fallback images. Stefan Reinauer
Hence drop the FALLBACK_ prefix Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6204 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16Get mptable OEM/product ID from kconfig variables.Uwe Hermann
We currently use "COREBOOT" unconditionally as the "OEM ID" in our mptable.c files, and hardcode the mainboard name in mptable.c like this: mptable_init(mc, "DK8-HTX ", LAPIC_ADDR); However, the spec says "OEM ID: A string that identifies the manufacturer of the system hardware." (Table 4-2, page 42) so "COREBOOT" doesn't match the spec, we should use the hardware vendor name. Thus, use CONFIG_MAINBOARD_VENDOR which we have already as the "OEM ID" (truncate/fill it to 8 characters as per spec). Also, use CONFIG_MAINBOARD_PART_NUMBER (the board name) as "product ID", and truncate/fill it to 12 characters as per spec, if needed. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13Compile cbmem.c instead of including it in romstage,Rudolf Marek
and do that only if resume is done. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6174 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08Move "select CACHE_AS_RAM" lines from boards into CPU socket.Uwe Hermann
All K8/Fam10h boards use CAR, so move the "select CACHE_AS_RAM" into the socket directories, and remove it from the individual boards. Do the same for Intel CPUs/sockets where all boards use CAR. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08second round name simplification. drop the <component>_ prefix.stepan
the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the <componentname>_ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08first round name simplification. drop the <component>_ prefix.stepan
the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the <componentname>_ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-07Get rid of some unneeded function prototypes in romstage.c files.Uwe Hermann
Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21Simplify a few code chunks, fix whitespace and indentation.Uwe Hermann
Also, remove some less useful comments, some dead code / unused functions. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21Drop excessive whitespace randomly sprinkled in romstage.c files.Uwe Hermann
Also drop some dead or useless code snippets. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1