summaryrefslogtreecommitdiff
path: root/src/mainboard/jetway/j7f24
AgeCommit message (Collapse)Author
2008-12-19I honestly have no idea if the previous use of the vt8235's serial functionsCorey Osgood
worked or not, but my board doesn't have COM1, and those function don't support using COM2, so I've changed auto.c to use the fintek f71805f functions, the fintek is the onboard super io. I also cleaned up a whitespace issue and unused variable. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3821 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-17One more little fix for the Jetway J7F[24], option tables can only be Corey Osgood
built in the normal image, not fallback. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3667 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-12For the jetway jf2/4 series of mainboards:Alex Mauer
* change the comment for device f.0 from "IDE" to "SATA" * turn on firewire device a.0 * turn on pata device f.1 * don't turn on the unusable device 10.5 (built-in vt8237 ethernet?) Signed-off-by: Alex Mauer <hawke@hawkesnest.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3577 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-10Add the "jetway j7f[24]*" mainboard. As compared to the Via Epia CN, thisAlex Mauer
changes the superio to a Fintek F71805F as described at http://www.coreboot.org/Jetway_J7F2_Build_Tutorial It also creates the mainboard tree for this series of motherboards (Jetway J7F2 and J7F4). I've tested it with one motherboard (J7F2WE1G3), and I believe it works with the others, as the differences among them are mostly trivial (processor speed, chipset and quantity of LAN cards, audio chipset, etc.). A list of the relevant motherboards with specs can be found at http://www.jetway.com.tw/jw/ipcboard_socket.asp?platid=16 The irq_tables.c is copied directly from the epia-cn, because the one generated by getpir with the factory BIOS did not work properly while the EPIA-CN one did. Minor changes on checkin to cope with moved romcc in latest revision. NOTE: This board is broken until the issue introduced in r3567 is resolved. Signed-off-by: Alex Mauer <hawke@hawkesnest.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3571 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1