| Age | Commit message (Collapse) | Author |
|---|
|
This change uses the newly added `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES`
Kconfig to enable USB4 resources and drops the configuration
in mainboard.
Change-Id: I707c5d63ea8c58e72126fe0d319ba81a99221ba5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Add new board variant to enable MCHP1727 Modular EC Card on RVP
BUG=b:179214042
BRANCH=none
TEST=emerge brya and verify that adlrvp_p_mchp images boot
Change-Id: I9dc96ad5c5db21fedbe480d19fcae8434d3bd169
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56839
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
FSP-S hides the PMC from the PCI bus when it runs, but there are still
initialization steps coreboot programs for the PMC. Therefore, change
all of the cannonlake mainboards to set the PMC as hidden in the
devicetree, which means the device will be skipped during enumeration,
but device callbacks are still issued as if the device were enabled.
TEST=Ran full patch train on google/dratini, disassembled SSDT and the
PEPD device matches what is in pep.asl. Also verified via dmesg that the
INT33A1 device is still initialized by the kernel.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib4a20ce9075ce7653388a5d3e281fe774bf89355
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I15203920546363466eef567136821b59dda763b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54648
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
These defines are copy-paste leftovers from Kunimitsu. However, neither
Saddle Brook nor KBLRVP use memory-down, so drop the unneeded defines.
Change-Id: I396aeaa634f619be7be0ee97c0cab1c682f53ff2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
The I2C #5 device is already disabled in the devicetree.
Change-Id: Ia4970dc07ef57e8184bce395a446974a22eddb08
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Disable devicetree devices disabled in the `SerialIoDevMode` array.
These devices get disabled by FSP-S, and coreboot doesn't see them.
Change-Id: I8dbb45c96eae5188e5999df9a458f06f6b196adf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
All KBLRVP variants select the `INTEL_LPSS_UART_FOR_CONSOLE` Kconfig
option and set `UART_FOR_CONSOLE` to `2`, so that UART #2 is used as
coreboot console. However, the LPSS console driver requires the LPSS
UART to be memory-mapped (and not I/O-mapped, like Super I/O UARTs).
KBLRVP variant RVP8 uses `PchSerialIoLegacyUart` for UART #2, which
makes FSP-S configure UART #2 in legacy, I/O-mapped mode. This most
likely results in the UART console not working after FSP-S has run.
This change updates RVP8 to use `PchSerialIoSkipInit` for UART #2, like
the other KBLRVP variants do.
Change-Id: Ic5c78f5895fe1dd5e7be6ef7aec3de6940dd2475
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
This is most likely a copy-paste remnant, and will never be needed for
RVP8: the SDXC device does not exist on PCH-H (and RVP8 uses a PCH-H).
Change-Id: I69059a88dcdb032beaab5fb03981dccbae0db02e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
The I2C #4 and I2C #5 devices do not exist on PCH-H. Disable the devices
using the PCH-H variants' overridetrees (the base devicetree enables I2C
#4), set the `SerialIoDevMode` entries to `PchSerialIoDisabled` and drop
inapplicable I2C #4 voltage settings.
Change-Id: I56f34fa2004993d2123ccd5c1008fd71682ec2bd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This change adds a new Kconfig `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES`
that can be selected by mainboard to reserve hotplug resources for
USB4 at the SoC level. `ADL_ENABLE_USB4_PCIE_RESOURCES` is dropped
from soc/intel/alderlake and instead the newly added Kconfig is now
used. This new Kconfig is added so that the same config can be used
across different platforms. In following changes, this Kconfig is
utilized by TGL as well.
Change-Id: Id7c359a0e255c43c2732f6cbe287bc7da14a46e3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
TEST=none
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I6346b087543217c78f87751051a4f38b23c566d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
The overrides set the options to the same value as drivers/intel/fsp2_0/
Kconfig does, so drop the overrides.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I53922786382a2e7d29b3df560a1998f41e1d2ea8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Normally, selecting FSP_USE_REPO will select FSP_FULL_FD which then will
configure the proper paths for FSP_M_FILE and FSP_S_FILE. The override
in these two boards caused FSP_M_FILE and FSP_S_FILE being empty despite
ADD_FSP_BINARIES being selected by FSP_USE_REPO which is an invalid case
that needs to be avoided, so remove the board-level override of those
two options.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I20c8cebea8327d59f0f33d05b824a74bf2121f4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
The ADD_FSP_BINARIES override in the mainboard's Kconfig caused this
option to not be selected when FSP_USE_REPO is selected. Remove the
override to fix this problem. These two boards are the only ones in tree
that had an override for this option, so now the ADD_FSP_BINARIES option
is only defined in drivers/intel/fsp2_0/Kconfig.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I23439f3134eef9460625addbff7efd64c5f65ae5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Add TPM IRQ config to gpio_m.c, so the TPM IRQ is not allocated
to I2C4.
BUG=NA
BRANCH=None
TEST= boot to os and check cat /proc/interrupts, cr50 SPI interrupt is assigned
and does not conflict with I2C.
CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7 CPU8 CPU9 CPU10 CPU11
0: 36 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 2-edge timer
1: 0 0 0 0 0 0 0 0 9 0 0 0 IO-APIC 1-edge i8042
8: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 8-edge rtc0
9: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 9-fasteoi acpi
14: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 14-fasteoi INTC1055:00
16: 0 0 0 0 0 0 0 0 0 0 4 0 IO-APIC 16-fasteoi intel-ipu6
22: 0 13 0 0 0 0 0 0 0 0 0 0 IO-APIC 22-fasteoi idma64.4, i801_smbus, ttyS0
37: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 37-fasteoi idma64.0, i2c_designware.0
38: 0 0 0 0 0 0 0 0 0 0 4 0 IO-APIC 38-fasteoi idma64.1, i2c_designware.1
41: 0 0 0 0 2274 0 0 0 0 0 0 0 IO-APIC 41-edge cr50_spi
42: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 42-fasteoi idma64.2, i2c_designware.2
43: 4 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 43-fasteoi idma64.3, i2c_designware.3
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: Id0f3885dec5a6f635254c233709090321491c739
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57102
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
CONFIG_DRIVERS_INTEL_MIPI_CAMERA and CONFIG_SOC_INTEL_COMMON_BLOCK_IPU
are getting selected for all ADLRVPs irrespective of ADL-P and ADL-M
(internal and external EC SKUs) hence, select those Kconfigs from
mainboard Kconfig rather Kconfig.name.
Also, select DRIVERS_INTEL_SOUNDWIRE as per alphabetical order.
TEST=No changes are seen while the .config file is getting auto
generated.
Change-Id: I62d5ec19c3364da79ebe7287b1b3d6eb2a0efca0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Set the `UserBd` FSP-M UPD to `BOARD_TYPE_DESKTOP` by default on PCH-H.
Remove now-redundant mainboard code to set the `UserBd` UPD.
Change-Id: I349abe5d89f562c158ce9baadbca2b2f56695846
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57261
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Specify the type of the `DIMM_SPD_SIZE` Kconfig symbol once.
Change-Id: I619833dbce6d2dbe414ed9b37f43196b4b52730e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
This fix will enable PCIe x1 slot for ADL-M LP4 and LP5 RVPs.
The BDF for this PCIe slot is pci is: 0000:00:1d.0
TEST = show device command:
$ lspci -s 00:19.0
expect this:
00:19.0 Serial bus controller [0c80]: Intel Corporation Device 51c5
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ia988fa0b5d8fefe68503b39843aab06c4229b36f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57053
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change follows other Intel SoCs common way to support SKUs with
bsp lapic_id != 0 by removing hardcoded lapic 0 from devicetree.cb and
allowing its detection at boottime. It completes support for HCV/DNV
after base SoC patch: commit ba936ce5db819d5ecb34e83a998b2390ecbdc4b9
soc/intel/denverton_ns: Ensure CPU device has a valid link
Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/YLMK2FBWWL6RKDNKBVZB3NJDYMEYHED7/
"A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538)."
Change-Id: I88f60f64d2beb2768ec9833de582d7901f456b11
Signed-off-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: King Sumo <kingsumos@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the
default by changing its enum value to 0 and remove its configuration
from all related devicetrees.
If `common_soc_config.chipset_lockdown` is not configured with
something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT`
is used.
Also, add a release note for the upcoming 4.15 release.
Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
This will add ACPI information to enable WACOM touchscreen.
TEST=Boot DUT and issue command:
$ ls -al /sys/bus/i2c/devices
WACOM PWB-D893 device should be listed and touchscreen should be functional.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I37c0831485135fda3284dda6b61f4825b7fc51a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
|
|
Make `mainboard_fill_spd_data` mandatory and adapt mainboards to define
this function accordingly.
Change-Id: Ic18c4c574e8c963bbb41c980f43bdbacc57735af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55806
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:187446498
TEST=Boot and verify memory trains at all the SaGv points through FSP
debug logs.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I883ae50b07e7b1d5554763fd79079d40b264b721
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
This reverts commit 68d8357dab55660058ad1ab8dca34fd03e0adbb5.
Reason for revert: Device NVS is expected by mainboard samus
in payload depthcharge:
https://chromium.googlesource.com/chromiumos/platform/depthcharge/+/932c6ba2704987c0db64dbdfe03c158482c7ab11/src/board/samus/board.c#60
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Icb5fa6da3412a51aae56c3658163e5b98d57bab3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
This patch enables eNEM flow for Alder Lake SoC hence drop INTEL_CAR_NEM
Kconfig from ADL-P RVP. ALDERLAKE_CAR_ENHANCED_NEM Kconfig will select all
relevant Kconfig required to enable eNEM for Alder Lake.
Additionally, select INTEL_CAR_NEM Kconfig for ADL-M RVPs from Kconfig.name.
BUG=b:168820083
TEST=Able to build and boot ADL-P RVP using eNEM mode.
Change-Id: I08561c8f50bbc4afe2bcdff4cc50e74d8fa2f68e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48345
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch decouples the selection of eNEM feature enablement from SoC
to ensure the ADLRVP does the validation first prior enabling this
feature on OEM/ODM reference designs.
BUG=b:168820083
TEST=No changing is being observed in .config with and without this CL.
Change-Id: I709185159d9869501b1d8e8d00f6d25ec77838bf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
For mainboard devicetree, it always have definition for enabling
cpu_cluster 0 which is required for all the variants.
Since it is SoC related settings, it's better to keep in chipset.cb
as a common setting for all the mainboards using the same SoC.
BUG=None
BRANCH=None
TEST=Change has no functional impact on the brya board.
Change-Id: I20bf1a87c7a9b343a86053692617c127a1a3250d
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56955
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
coreboot always assumes that BSP APIC ID will be 0 and core enumeration
logic will look for lapic id from the mainboard.
As per Intel 64 and IA-32 Architectures Software Developer’s Manual
Volume 3: 8.4.1 BSP and AP Processors, this assumption might
not hold true and we may have any other core as BSP. To handle this,
we need to remove hardcoding of APIC ID 0 from mainboard.
BUG=None
BRANCH=None
TEST=Check if there is no functional impact on the board.
Change-Id: I175ae26f934f08e125bea7cc3195bdb5792c2360
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56954
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add Kconfig options and enable TPM device in devicetree
BUG=None
TEST=Booted the image and checked the successful TPM
communication in verstage,romstage & ramstage from
coreboot logs.
Signed-off-by: Thejaswani Puta thejaswani.putta@intel.com <thejaswani.putta@intel.com>
Change-Id: Icaedf9f17e35e82c35cbabd6d2938c167e42e9e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
|
|
DDR5 Maple Ridge SKU (Board ID 0x16) uses a Memory down DIMM
configuration.
TEST=Boot DDR5 MR SKU to OS.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b7a96b5534d8b80776aa7578ce7c13181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56881
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Naming spd_info struct based on memory topology helps in reuse of
code.
lp4_lp5_spd_info -> memory_down_spd_info
ddr4_ddr5_spd_info -> dimm_module_spd_info
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b7a66b5524d8b80776ab7578ce7b13181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
With current setting Display audio codec probe fails.
Hence HDMI/DP audio fails.
Earlier, with FSP 2037 was used the mode was incorrectly programmed to 4T
This setting was carried ahead with below change:
Commit : 50f8b4ebdd7db8077b87ab7686637599c9d93af3
The issue was fixed in later FSPs and with current
FSP v2237, we need to set the TMODE to 8T as per spec.
TEST=Verify HDMI/DP Playback on ADL P RVP
Fixes: 50f8b4ebdd7db8077b87ab7686637599c9d93af3
(soc/intel/alderlake: Add enum for HDA audio configuration)
Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
Change-Id: Ia39a33f5da2fea0dc2eaf4eae45999a711c61c33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56208
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add dynamic power limits selection mechanism for aldrvp board.
BUG=None
BRANCH=None
TEST=Build FW and test on adlrvp with DPTF tool
On adlrvp (282):
Overriding DPTF power limits PL1 (3000, 15000) PL2 (55000, 55000)
On adlrvp (682):
Overriding DPTF power limits PL1 (5000, 45000) PL2 (115000, 115000)
Change-Id: Id1aef0125c6e1e105665172f19bda271e232d94f
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
For mainboard devicetree, it always have definition for enabling
cpu_cluster 0 which is required for all the variants.
Since it is SoC related settings, it's better to keep in chipset.cb
as a common setting for all the mainboards using the same SoC.
BUG=None
BRANCH=None
TEST=Change has no functional impact on the brya board.
Change-Id: I8f7c3184b62f8d84ca4605fb9f2a1cc569f1f964
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56853
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
coreboot always assumes that BSP APIC ID will be 0 and core enumeration
logic will look for lapic id from the mainboard.
As per Intel 64 and IA-32 Architectures Software Developer’s Manual
Volume 3: 8.4.1 BSP and AP Processors, this assumption might
not hold true and we may have any other core as BSP. To handle this,
we need to remove hardcoding of APIC ID 0 from mainboard.
BUG=None
BRANCH=None
TEST=Check if there is no functional impact on the board.
Change-Id: Ibc60494b0032a3139c1e6c79251fb2da750c8de8
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
This will enable to include multiple VBT binaries in a single image
and load corresponding file according to HW configuration.
BUG=None
TEST= Boot device on LP5/LP4, corresponding VBT file should be loaded.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Iace0e5e0783b2074393a537da8cc645102d2acda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55969
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
coreboot always assumes that BSP APIC ID will be 0 and core enumeration
logic will look for lapic id from the mainboard.
As per Intel 64 and IA-32 Architectures Software Developer’s Manual
Volume 3: 8.4.1 BSP and AP Processors, this assumption might
not hold true and we may have any other core as BSP. To handle this,
we need to remove hardcoding of APIC ID 0 from mainboard.
BUG=None
BRANCH=None
TEST=Check if there is no functional impact on the board.
Change-Id: I726d70b4ffc35a28a654abbd20c866f1410e1aee
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
This feature was added in ADL-M RVP for discovering correct
audio topology using OEM string e.g., "ADL_MAX98373_ALC5682I_I2S"
for discovering boards having audio expansion card
Bug=None
Test= With CBI FW_CONFIG set to 0x100
localhost /home/root # dmidecode -t 11
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.
Handle 0x0009, DMI type 11, 5 bytes
OEM Strings
String 1: ADL_MAX98373_ALC5682I_I2S
Change-Id: I05887d9d654eae6d9d2da731d8ab4cf4a05c287f
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55368
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I80f11b8f0c2a1fdccbc322c3c4783c61684ff37a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55634
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Select `INTEL_LPSS_UART_FOR_CONSOLE` to allow using PCH UART 2 as
coreboot console. Also, simplify `UART_FOR_CONSOLE` defaults.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I853777116fc541e5dc31f3ca8673f8bf66c7c9e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Specify the type of the `VARIANT_DIR` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: Iea2f992a59e41e00fec3cdc9d6a13b5f3ab0a437
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56558
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Specify the type of the `FMDFILE` Kconfig symbol once instead of doing
so on each and every mainboard.
Change-Id: I810bd3fe8d42102586db6c2c58b7037a60189257
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56557
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Specify the type of the `OVERRIDE_DEVICETREE` Kconfig symbol once
instead of doing so on each and every mainboard.
Change-Id: I4cbf4e318a30f0cf75aa8690e7454b9caa115c9d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56556
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Specify the type of the `DEVICETREE` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: If68f11a5ceaa67a3e8218f89e1138c247ebb9a25
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56555
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once
instead of doing so on each and every mainboard.
Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol
more than once. This is done in `src/Kconfig`, along with its prompt.
Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Remove redundant type, prompt and help text, and replace `depends on`
clause with conditional default to allow specifying a FMAP when vboot
is not selected.
Change-Id: I37ddab3a27e304e810ea55f13821d755bb70cb4b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56551
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Currently, internal flashing is not possible due to FSP lockdown. Thus
let coreboot do chipset lockdown on all variants.
Change-Id: Ib25a0543bfee0889dce071f3b01725daabd0a0eb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56407
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Provide an option to set xHCI LFPS period sampling off time
(SS_U3_LFPS_PRDC_SAMPLING_OFFTIME_CTRL in JSL EDS revision 2.0).
If the option is set in the devicetree, the bits[7:4] in
xHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated.
The host will sample LFPS for U3 wake-up detection when suspended, but
it doesn't sample LFPS at all time due to power management, the
default xHCI LFPS period sampling off time is 9ms. If the xHCI LFPS
period sampling off time is not 0ms, the host may miss the
device-initiated U3 wake-up and causes some kind of race condition for
U3 wake-up between the host and the device.
BUG=b:187801363, b:191426542
TEST=build coreboot with xhci_lfps_sampling_offtime_ms and flash
the image to the device. Run following command to check the bits[7:4]:
iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Ben Kao <ben.kao@intel.com>
Change-Id: I0e13b7f51771dc185a105c5a84a8e377ee4d7d73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
This patch sets the optimized FIVR configs for ehlcrb customized
based on the performance measurements to achieve the better power
savings in sleep states.
- Enable the external V1p05, Vnn, VnnSx rails in S0i3, S3, S4, S5
states.
- Update the supported voltage states.
- Update max supported current, voltage transition time and RFI
spread spectrum.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I1e30ff6d84bfe078fcce0f968fce6aaab7fd575b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55981
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
- Add configurability using FW_CONFIG field in CBI, to
enable/disable I2S codec support for MAX98373 codecs
- AUDIO=ADL_MAX98373_ALC5682I_I2S: enable max98373 codec
using expansion board
Bug=None
Test=With CBI FW_CONFIG set to 0x100, check I2S audio output
on expansion card
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: If2649647e58c5f30e2b539d534adf2a4e68f4fda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52221
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.
Change-Id: I411f4f2c237a9e2d39038ee30f2957698ee053bd
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
The patch updates PMC Descriptor which is part of Descriptor Region if
system equipped with Alder lake A0 silicon. This change allows to use
unified Descriptor Region for Alder lake A0(CPU ID:0x906a0) and B0
(CPUD ID:0x906a1) silicons. The change has to be reverted before EOM is
enableda on the system.
BUG=B:187431859
TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon
if not updated.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2a1f60fda7575212bb694fc423bd229452515903
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
Disable tcss_xdci as it is not used.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I94102240b13d2b96e0295f41bc2b0ba078faf342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
|
|
Clean up lockdown configuration and move it to the baseboard's
devicetree.
Since most of the mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, use it
for the rvp8 variant for consistency as well.
Built intel/rvp11 with `BUILD_TIMELESS=1` and coreboot.rom remains
identical. intel/rvp8 changes, as expected.
Change-Id: I78e847c321c61c3a974b26f30bc2823ff84df651
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56212
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I4b5e0992494949bcb2fbda1361e0118c087a437a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56211
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch enables CONFIG_VBOOT_EARLY_EC_SYNC.
EC software sync will be performed in romstage.
BUG=None
BRANCH=None
TEST=Verify EC software sync works on adlrvp_m
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: I3a13094e5da2f672a6789fe86528de44e909045e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56154
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update Power Limit2 (PL2) minimum value to the same as maximum value.
DTT does not throttle PL2, so this minimum value change here does not
impact any existing behavior on the system.
BUG=None
BRANCH=None
TEST=Build and test on tglrvp system
Change-Id: I6bbbfa8e43a241df721b91425294983c1d561f2c
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
camera ACPI
This change updates device tree to enable SSDT generation for
world facing camera and user facing camera for ADLRVP.
Also reverts DSDT changes related to both camera.
TEST=Build and Boot aldrvp check i2c enumeration and output of media-ctl
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I39f82dc9eb91496d80479ae3f59ca5e03402a599
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
|
|
ACPI
This change updates device tree to enable SSDT generation for
world facing camera and user facing camera for ADLRVP.
Also reverts DSDT changes related to both camera.
TEST=Build and Boot aldrvp check i2c enumeration and output of media-ctl
Compared SSDT with this patch against DSDT without this patch, they are same
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I08834bbcf80dc46737de07f69a2402ed6bf93d4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
|
|
This patch sets the optimized FIVR configuration for adlrvp cutomized
based on the pnp measurements to achieve the better power savings in
sleep states.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 states.
* Update the supported voltage states.
* Set the ICC max to 500mA for v1p05 and vnn.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I83e6910502d5cf9d4c26fa581272f59ac483ae19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
Enable PCH GBE with following changes:
1. Configure PCH GBE related FSP UPD flags
2. Use EHL own GBE ACPI instead of common code version due to
different B:D.F from the usual GBE
3. Add kconfig PMC_EPOC to use the PMC XTAL read function
Due to EHL GBE comes with time sensitive networking (TSN)
capability integrated, EHL FSP is using 'PchTsn' instead of the
usual 'PchLan' naming convention across the board.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I6b0108e892064e804693a34e360034ae7dbee68f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
google_chromeec_get_event returns 0 for no event. Return
EC_HOST_EVENT_NONE=0 to improve readability.
BUG=b:184074997
TEST=Build and boot guybrush without error
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Ic08ed9ccdd7c0023d0fe8b641fcf60dca495a242
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This provide a more consistent mechanism to enable corresponding USB
TCSS port.
BUG=b:182960979
TEST=Boot device, Type C port should operate correctly.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Iadc0df2e6e19a5afacbb7db1ae0bc7546dbcdc1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55772
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch updates mainboard_memory_init_params() function argument from
FSPM_UPD to FSP_M_CONFIG. Ideally mainboard_memory_init_params()
function don't need to override anything other than FSP_M_CONFIG UPDs
hence passing config block alone rather passing entire FSP-M UPD
structure.
Change-Id: I238870478a1427918abf888d71ba9c9fa80d3427
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Set "SerialIoUartMode" for UART0 as PchSerialIoSkipInit
Change-Id: Idc7da7bf38634c04b0f4acd4c7c2ea9fa88545e5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55207
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
dmidecode output should match with the CrOS kernel updated string.
TEST=dmidecode grep "Manufacturer" = Intel Corporation
dmidecode grep "Product name" = Alder Lake Client Platform
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I7cce423de624e7056e88b52a1443c554fd9123bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51408
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change the default rom size to 32MB and remove chromeos.fmd
because Chrome OS is not supported on EHL for now.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I49d9404eb901087037b5423a4a503c5271e14138
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55554
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Due to latest corresponding UPD filling implementation, this is not
required.
This patch fixed the brokenness caused by
Commit hash b10afbd2e2a8326fb21dc726a6c2bd53b06eb010.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I49e434f7bbafcb148e82202697e87c3e4268d7b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function
(NF1), this causes redundancy with legacy HPD interruption.
This change configures GPP_A19 and GPP_A20 to be no connection and
disables DdiPort1Hpd and DdiPort2Hpd.
BUG=None
TEST=Boot to kernel and verified no kernel HPD pins assertion message.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I80ef40a1aca19cd6ad56219175d2fd40890a393d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sanrio Alvares <sanrio.alvares@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
|
|
Use hostbridge.asl from Haswell instead of Broadwell. Both files are
equivalent. Then, drop the now-unused hostbridge.asl from Broadwell.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I87d51727b75a9c59e2f5f3ba8d48c575ce93c78c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Disable all display related UPDs if IGD is not enabled as FSP
don't need to perform display port initialization while IGD itself
is disabled else assign UPDs based on devicetree config.
TEST=Dump FSP-M display related UPDs with IGD enable and disable
to ensure patch integrity.
Change-Id: I0479904141dfc5e707679109aa18b7ef4264cf96
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
The same functionality can be provided through a runtime-generated SSDT.
The remaining parts of device NVS are removed in a follow-up.
Since the SSDTs are only loaded after the DSDT (if loaded at all), using
SSDT-provided objects outside method bodies is not possible: the objects
are not yet in OSPM's ACPI namespace, which causes in ACPI errors. Owing
to this, the operation regions used by the _PS0 and _PS3 methods need to
be moved into the SSDT, as they depend on the SSDT-provided BAR1 values.
Tested on out-of-tree Compal LA-A992P, generated SSDT disassembles with
no errors and contains expected values. Linux does not complain either.
Change-Id: I89fb658fbb10a8769ebea2e6535c45cd7c212d06
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Add support for Maple Ridge DDR5 SKU with boardid 0x16
TEST=Verified build for ADL-P Chrome RVP
Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com>
Change-Id: I9f0e9072f5866b60fb8463bb90f61915c78568db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.corp-partner.google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
|
|
Split parameter '(devfn << 2) | intx' to 'devfn, intx'.
Formatted with 'spatch --max-width 96'
Change-Id: I17a6b3919b6e55aaa7ca2873ca713b36ebe7d3a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55285
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Read I/O APIC ID and version from hardware registers.
With coccinelle below, and minor fixups.
@ r1 @
expression E1, E2, E3, E4;
typedef u8;
@@
-smp_write_ioapic(E1, E2, E3, E4);
+u8 ioapic_id = smp_write_ioapic_from_hw(E1, E4);
@ r2 @
expression E1, E2, E3, E4;
@@
-mptable_add_isa_interrupts(E1, E2, E3, E4)
+mptable_add_isa_interrupts(E1, E2, ioapic_id, E4)
@ r3 @
expression E1, E2, E3, E4, E5, E6, E7;
@@
-smp_write_pci_intsrc(E1, E2, E3, E4, E5, E6, E7)
+smp_write_pci_intsrc(E1, E2, E3, E4, E5, ioapic_id, E7)
@ r4 @
symbol mp_INT;
expression E1, E3, E4, E5, E6, E7;
@@
-smp_write_intsrc(E1, mp_INT, E3, E4, E5, E6, E7)
+smp_write_intsrc(E1, mp_INT, E3, E4, E5, ioapic_id, E7)
Change-Id: I20799f0c09cf0292661e1f3cb93373b2c68b7314
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Note that there are assumptions about LAPIC MMIO location
in both AMD and Intel sources in coreboot proper.
Change-Id: I2c668f5f9b93d170351c00d77d003c230900e0b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55194
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Most of the Kconfig files for Intel SOC devices define the MAX_CPUS
value within src/soc/intel/*/Kconfig.
Move the definition there for Tiger Lake and remove from the mainboard
Kconfig files.
Signed-off-by: Andy Pont <andy.pont@sdcsystems.com>
Change-Id: If145b9eb5d99821f4ce513118e4417d05f821ef5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Power limits (PL1 and PL2) depend on the specific SKU of the CPU.
By expanding the SoC chip config power_limits_config member to
an array indexed by ADL_*_POWER_LIMITS_*_CORE macros, the
appropriate power limits are applied. Using this the correct
set of power limits are being selected from the array based on
system agent PCI ID. Based on this, chipset.cb file contains
the set of power limits being used by varieties of ADL boards.
These power limit values are as per document 619501.
BUG=None
BRANCH=None
TEST=Built and verified the following console output on below boards
On adlrvp (482):
CPU PL1 = 28 Watts
CPU PL2 = 64 Watts
On adlrvp (682):
CPU PL1 = 45 Watts
CPU PL2 = 115 Watts
On brya (282):
CPU PL1 = 15 Watts
CPU PL2 = 55 Watts
Change-Id: Ic1676e2b4d611cdc85e770f131d5b6d5ecd180be
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
|
|
IO MWAIT redirection is not enabled, and C-states are reported using the
_CST ACPI object, which overrides the P_LVLx values.
Change-Id: I737bd58bcda3e7c5f6591e4c2309530ff035e2c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
If unspecified, chipset code already uses 101, and 0x65 == 101.
Change-Id: I524ca492fa577003df23017756f74a455582132f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Use the device aliases provided by alderlake chipset.cb instead of
the raw pci device+function. Take advantage of the default states
in chipset.cb and only list the devices that are enabled for all
shadowmountain board variants.
TEST=Dump devicetree device enable list without and with this CL, no
difference observed.
Change-Id: I2b769d653ad8ad8ff069a0787d00ff33ead5c912
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Use the device aliases provided by alderlake chipset.cb instead of
the raw pci device+function. Take advantage of the default states
in chipset.cb and only list the devices that are enabled for all
different adlrvp boards.
TEST=Dump devicetree device enable list without and with this CL, no
difference observed.
Change-Id: Ib9e82d953416c076588974f3167d00ae96f01bb5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55205
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I095394d9a79506346b8464c850d03cbd8ce2b812
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55221
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Further add initial Silicon UPD storage settings:
- SATA
- SD card
- eMMC
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
|
|
Further add initial Silicon UPD settings for:
- PCIe root ports
- USB
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I60afb78a7997b8465dd6318f3abee28f95a65100
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55034
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Further add initial silicon UPD settings for:
- graphics & display
- chipset lockdown
- PAVP
- legacy timer
- PCH master gating control
- HECI
This CL also enables HECI 1 in devicetree.cb.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
|
|
BUG=none
TEST=Use command $ lspci -vv
LTR+ is listed on DevCtl2
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: If65d08a46b9e7304fbe4b92b7f1e6d4e08c599e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54492
Reviewed-by: Ryan A Albazzaz <ryan.a.albazzaz@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add Silicon upd settings for LPSS (GSPI/UART/I2C).
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
TEST=Boot to OS and verify acpi tables.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I3c78ac44afa3515acef9ea2d59f22f95e6b45e90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54490
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com>
Reviewed-by: John Zhao <john.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Upload the FSP-M UPD configs. This CL also updated the chip.h and
devicetree.cb with the relevant variables and configs.
This CL also updated the GPIO related settings (PMC & SD card) in
devicetree.cb.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: If6321064b37535b390cf3dd7c41a719c598a0cd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
|
|
These PCIe and DMA ports are not available for adlrvp_m.
BUG=none
TEST=Boot device
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Ic568c692fbb82fb3fc70c0cafc2328f8fa2cd74d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Initial upload of the GPIO configs for EHL CRB.
This CL also includes the UART GPIO configs in early GPIO table.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ied4cbb34149b0b837597c0fc17dc5956f3ca409e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
This changes updates mainboard properties by adding DFP number and
power_gpio for each DFP.
BUG=b:186521258
TEST=None
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I29480bf77f7df9890bef64a5f9f02074a34dc131
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Along with upstream kernel for Retimer firmware update, coreboot defines
power control for each DFP respectively under host router. This change
removes the power_gpio from the baseboard. Individual DFPx power_gpio
will be added once the dependent definition is complete.
BUG=b:186521258
TEST=Build image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I819d2900afabbfdb2713fa8eee35d3c90cb904fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Most boards use `device lapic 0 on` with zero written in decimal.
For the sake of consistency, update the remaining boards to follow suit.
Change-Id: I1d3b1ac107e33aae11189cdd5e719b8e48b10f08
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Most boards use `device domain 0 on` with zero written in decimal.
For the sake of consistency, update the remaining boards to follow suit.
Change-Id: I6e2f0a19d57cfe6fc4e4ac4d14310133ad6b01d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
