summaryrefslogtreecommitdiff
path: root/src/mainboard/intel
AgeCommit message (Collapse)Author
2021-04-10mb/intel/shadowmountain: Enable Bluetooth config in the devicetreeSridhar Siricilla
The patch enables Bluetooth config in the devicetree and removes non-existent Bluetooth PCI interface. TEST=Verified by checking Garfield Peak controller's PID:VID(8087:0033) in the lsusb ouput. Output of lsusb: Bus 004 Device 003: ID 0bda:8153 Realtek Semiconductor Corp. USB 10/100/1000 LAN Bus 004 Device 002: ID 0bda:0411 Realtek Semiconductor Corp. 4-Port USB 3.0 Hub Bus 004 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub Bus 003 Device 003: ID 0781:55a9 SanDisk Corp. Dual Drive Bus 003 Device 004: ID 413c:2113 Dell Computer Corp. Dell KB216 Wired Keyboard Bus 003 Device 002: ID 0bda:5411 Realtek Semiconductor Corp. 4-Port USB 2.0 Hub Bus 003 Device 005: ID 8087:0033 Intel Corp. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I7a54d344ef1b0418bee56e7308977a61604b954a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52182 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-09mb/intel/adlrvp: Enable HECI1 communicationSridhar Siricilla
The patch enables HECI1 interface to allow OS applications to communicate with CSE. BUG=None TEST=Build and boot ADLRVP. Run lspci and check pcie device (00:16.0) Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I34ff842481bdfc7933a76555ff0fd70f4fbbb9a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-04-09mb/{google/jecht,intel/wtm2}: Remove NOOP APM finalize callArthur Heymans
The intel/soc/broadwell smihandler has no handler for this APM call. Change-Id: I2bcec7cce00d433a197a9e2fb01434a2998e1452 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52167 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06mb/intel/adlrvp: Update iDisp Link UPD settingsFrancois Toguo
This changes updates the iDisp-Link T-mode to 8T required for ADL-M. The update is made because the HW on ADL now supports 8T mode. BUG=None TEST= build and boot ADL-M RVP and verify HDMI/DP audio playback. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: I9d0bf7dc76348f7e184e8496f042badc30bf3211 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51353 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06mb/intel/adlrvp: Enable Camera in ADL-M RVPVarshit Pandya
1. Configure Power Enable, Reset and Clock GPIO for both camera 2. Use same ASL code as ADL-P RVP Configure RST, PWR_EN and IMGCLKOUT signals for WFC and UFC TEST=Build, Boot and Verify streaming in both Camera Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: I70636eaa8d9bdf23d649e811b3ff4f33b1bc604e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50265 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06mb/intel/shadowmountain: Add Cr50 supportAamir Bohra
This patch includes changes to add Cr50 support over GSPI0. BUG=b:175579964 TEST=Verify TPM init is done and boots to kernel Change-Id: I33f7427d1675190f65acf14679be93546e6db69a Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51086 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-02mb/intel/adlrvp: Update VBT filenamesTim Wawrzynczak
These files were just renamed to put `adlrvp` in between `vbt` and the memory technology type. Change-Id: Icefbac462d0ec9c660541e9cf44686d6dcf82dfd Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52032 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28mb/intel/adlrvp_m: Enable ADL-M RVP LP5 memory configurationMaulik V Vaghela
List of changes: 1. Add correct board Id for ADL-M LP5 configuration 2. Add spd hex files for LP5 Micron part 3. Update memory.c file with correct Dq-dqs and byte mapping for LP5 BUG=None BRANCH=None TEST=Build is successful for ADL-M RVP Change-Id: I0bbd3f5b56bf7fbe918cc599d32a01dcae896ddd Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2021-03-28mb/intel/adlrvp_m: Enable ADL_M RVP LP4 memory configurationMaulik V Vaghela
List of changes: 1. Add board Ids for ADL-M LP4 configuration 2. Add spd hex files for LP4 configuration 3. Update memory.c file with correct Dq-dqs and byte mapping for LP4 BUG=None BRANCH=None TEST=Build and boot is successful for ADL M LP4 RVP Change-Id: Id817faee3fff2a8a911ebda35774dfb6ddc5524b Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50257 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28mb/intel/adlrvp: Configure GPIOs for ADLRVP-MVarshit Pandya
List of changes: 1. Add separate file for ADL-M GPIOs 2. Configure GPIOs as per the schematics of ADL-M RVP TEST=Able to build ADL-M Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: I03a532f69f42db723b976a0f7b0acf6f4b98e354 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2021-03-28mb/intel/shadowwmountain: Enable CSE Lite SKU for shadowmountainSridhar Siricilla
During the initial phases, the development and validation teams have to deal with both Consumer SKU and Lite SKU firmware. Having the support for CSE Lite enabled by default in coreboot helps in integrating both the SKUs. With this we only have to interchange the CSE region in the full BIOS image without having to worry about Kconfigs. Eases the build and integration flow. TEST=Verified build for Shadowmountain Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I2ebf4da1b8c1df2e9c43b6e3bb688a9f8db652d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51496 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28mb/intel/adlrvp: Enable CSE Lite SKUSridhar Siricilla
During the initial phases, the development and validation teams have to deal with both Consumer SKU and Lite SKU firmware. Having the support for CSE Lite enabled by default in coreboot helps in integrating both the SKUs. With this we only have to interchange the CSE region in the full BIOS image without having to worry about Kconfigs. Eases the build and integration flow. TEST= Built and booted on ADL-P LP4 RVP Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ia92c7b71c69a23104ace9fc53fd39f01120fa751 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51567 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-27mb/intel/dcp847ske: Drop useless MCHBAR writesAngel Pons
There's no need to write the GDCRTRAININGRESULT registers after raminit. Change-Id: If604920fe7a3bee96f72f8aff5e96f0e25548f18 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50534 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-27mb/intel/adlrvp: Allow GPIO PM override to disable dynamic GPIO PMSubrata Banik
This patch allows overriding GPIO PM miscconfig register for each GPIO community to avoid dynamic clock gating. TEST=Dump GPIO Community MISCCFG register to ensure all Bit [7:0] are set to '0'. Change-Id: I9aca9cb0641e2731c028ea5ed76c563da3400b74 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-26mb/intel/shadowmountain: Disable the unused CPU PCIe RPV Sowmya
This patch disables the unsued CPU PCIe RP for shadowmountain. TEST= Boot shadowmountain and verify the device is disabled. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Ide2badb06178fca8ff5cf51d8573a14635e190cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/51772 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-26mb/intel/adlrvp: Remove static VBT stitchingMaulik V Vaghela
Currently, we used to stitch extra VBT files to ADLRVP build using Makefile. With enablement of emerge build, we should be able to integrate more than 1 VBT binaries using ebuild. This removing these lines to avoid compilation issues in emerge builds BUG=None BRANCH=None TEST=Check if compilation passes on emerge build. Stitched additional VBT files using emerge and checked that coreboot picks up correct VBT. Change-Id: I69f1cc6c07415515ff85180fdd7cc5de11b4d805 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-03-26soc/intel/alderlake: Add provision to override Rcomp settingsSubrata Banik
Add function to allow overriding the RcompResistor and RcompTarget UPDs from mainboard if required. Mainboard users can pass required rcomp from memory.c file. Refactor ddr_config structure to take out rcomp related variable outside for all memory type to override if required. BUG=b:182772421 TEST=Able to override the default RcompResistor and RcompTarget values. Change-Id: Ie8528bbf0517728534d47f9adaabfc9a2c469609 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-26soc/intel/alderlake: Align RcompResistor definition as per MRCSubrata Banik
List of changes: 1. Alder Lake MRC is expecting a RcompResistor value of word width. Reference RCOMP resistors on motherboard are ~ 100 Ohms but coreboot is passing an array of RcompResistor which is not completely in use. Note: Rcomp resistor value represents rcomp resistor attached to the DDR_COMP pins on the SoC. 2. Also, remove usage of '&' with memcpy the required value into RcompTarget array. 3. Also, update RcompResistor value for ADLRVP. BUG=b:183341229 TEST=Enable FSP debug log to verify the override value for RcompResistor is reflecting correctly. Change-Id: I69c7cec55b65036fc039c33374a3fd363ef7004e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-25nb/intel/haswell: Decouple mainboard USB config from MRCAngel Pons
With this change, only raminit.c uses pei_data.h definitions. With MRC cornered, making it optional is just a matter of writing a replacement. USB config definitions will be moved to Lynx Point code in a follow-up. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: I4bc405213e9b0828d9ced18677335533c7dd381d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-24mb/intel/adlrvp: Enable CnviBtAudioOffloadUsha P
This change enables CnviBtAudioOffload. FSP is invoked to configure BT over USB and BT I2S pins for cAVS connection. BUG=None TEST=Verified BT offload working on ADL RVP Signed-off-by: Usha P <usha.p@intel.corp-partner.google.com> Change-Id: I1185a6c2295bae7d469be4da86502506adbeb8cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/51032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-03-23nb/intel/haswell: Use unshifted SPD addresses in mainboardsAngel Pons
It's common to use the raw, unshifted I2C address in coreboot. Adapt mainboards accordingly and perform the shift in MRC glue code. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: I4e4978772744ea27f4c5a88def60a8ded66520e1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51458 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22lynxpoint/broadwell: Rename LP GPIO config globalAngel Pons
Do not use the same name as the non-LP GPIO config. This allows checking at build-time that a mainboard uses the correct GPIO config format. Without this commit, there are no build-time errors when using the wrong format of GPIO config, but there would be undefined behavior at runtime. Tested by trying to build asrock/b85m_pro4 and hp/folio_9480m after toggling the `INTEL_LYNXPOINT_LP` Kconfig option (and trimming down the USB config arrays for asrock/b85m_pro4). In both cases, building failed because the necessary GPIO config global is not defined, as expected. Change-Id: Ib06507ef8179da22bdb27593daf972e788051f3a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51661 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20mainboard/: Register chipset_lockdown on xeon_sp mainboardsMarc Jones
Set chipset_lockdown in devicetree for recommended security settings. Change-Id: Ie27450dd32463243b1456932a1d39d40afa81da1 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51388 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19nb/intel/haswell: Consolidate memory-down SPD handlingAngel Pons
Mainboards do not need to know about `pei_data` to tell northbridge code where to find the SPD data. Adjust `mb_get_spd_map` to take a pointer to a struct instead of an array, and update all the mainboards accordingly. Currently, the only board with memory-down in the tree is google/slippy. Mainboard code now obtains the SPD index in `mb_get_spd_map` and adjusts the channel population accordingly. Then, northbridge code reads the SPD file and uses the index that was read in `mb_get_spd_map`, and copies it to channel 0 slot 0 unconditionally. MRC only uses the first position of the `spd_data` array, and ignores the other positions. In coreboot code, `setup_sdram_meminfo` uses the data of each SPD index, so `copy_spd` has to account for this. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: Ibaed5c6de9853db6abd08f53bbfda8800d207c3e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51448 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17spd_bin: Replace get_spd_cbfs_rdev() with spd_cbfs_map()Julius Werner
In pursuit of the goal of eliminating the proliferation of raw region devices to represent CBFS files outside of the CBFS core code, this patch removes the get_spd_cbfs_rdev() API and instead replaces it with spd_cbfs_map() which will find and map the SPD file in one go and return a pointer to the relevant section. (This makes it impossible to unmap the mapping again, which all but one of the users didn't bother to do anyway since the API is only used on platforms with memory-mapped flash. Presumably this will stay that way in the future so this is not something worth worrying about.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Iec7571bec809f2f0712e7a97b4c853b8b40702d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17mb/intel/shadowmountain: Update HDMI audio mode to 8TSugnan Prabhu S
This patch sets the HDMI audio mode to 8T as required by the latest FSP version v2081_02 TEST: HDMI audio codecs detection is failing without this change. Change-Id: Ie5a825da7d199c9ee61e64d8f4ee7dec28fdaacd Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-03-17mb/intel/shadowmountain: Disable xDCISugnan Prabhu S
This patch disables the xDCI which is causing PC8 to PC10 state transitions during sleep. TEST: Confirmed that the transition is happening with this change. Change-Id: I9bbf7b52c36954600d7e66f9b03fad39b8881a5f Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2021-03-15mb/intel/tglrvp: Enable RTD3 for WWANBora Guvendik
Enable the PCIe RTD3 driver for WWAN device attached to PCIe Root Port 4 and provide the reset GPIO / src clk pin. BUG=none TEST=Boot to OS, verify the link is in L2 state during S0ix. Change-Id: I669e02bd02e3af878648a6f3cf4fbb4d06c9857f Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2021-03-15mb/intel/tglrvp/variants: Disable non-existing BT PCI interface and add BT flagCliff Huang
Remove the CNVi BT PCI config and add BT flag. There is no PCI host interface in this version of CNVi. TEST: BT is checked using 'lsusb -d 8087:0026' from OS to make sure BT is enumerated. Change-Id: I8de5615235f24e6169bf67dbbadb92e69437bc4e Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50899 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/intel/adlrvp: Disable non-existing BT PCI interface and add BT flagCliff Huang
Remove the CNVi Bt PCI config and add Bt flag. There is no PCI host interface in this version of CNVi. TEST: BT is checked using 'lsusb -d 8087:0026' from OS. Change-Id: I17c3e2761f91fb397d140d1954b6d4b451c4c603 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUsMeera Ravindranath
Add support to pick the right vbt from cbfs according to SKU-ID. Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15mb/intel/shadowmountain: Add ACPI entry for BT reset GPIOAamir Bohra
Change-Id: Ia9e57f34eceaf1925dc5e3ffa6370ba0241447a4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2021-03-15mb/intel/adlrvp: Select ADL_ENABLE_USB4_PCIE_RESOURCESTim Wawrzynczak
This change select the Kconfig to pre-allocate the Intel-recommended bus and memory resources per-PCIe TBT root port for the adlrvp mainboard. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic56ebab02e50a466662a07d122d8f40eaf16b54b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51461 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12soc/intel/braswell: Factor out common `acpi_fill_madt`Angel Pons
Function is identical for all mainboards, so factor it out. Change-Id: Ibe08fa7ae19bfc238d09158309f0a9fdb31ad21c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50028 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12mb/intel/adlrvp: do UART pad config at board-levelMichael Niewöhner
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: I55815a824ea3a77e6e603ba4beb17457f37c48f5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-12mb/intel/shadowmountain: Enable Type-C subsystemV Sowmya
This patch adds the changes to enable the TCSS. BUG=b:175808146 TEST= Boot shadowmountain board, Test the functionality of the Type-C ports on both the mainboard and daughterboard by plugging in the Type-C devices and verified the devices are detected via EC console and in the OS. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Ieaf1170ca718a14d24b773a4a85516e0bbfbb569 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51026 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03mb/*/*: Don't select PCIEXP_HOTPLUGArthur Heymans
PCIEXP_HOTPLUG has a prompt and as such is not supposed to be forced. Just change the default value to 'y'. Change-Id: Ie4248700f5ab5168bff551b740d347713273763c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03mb/{intel/d510mo,foxconn/d41s}/devicetree.cb: Remove PEG deviceArthur Heymans
Pineview does not support PEG. Change-Id: Ib0006dbd54e6f2031b97ed11ce61407ffcfa6244 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03mb/intel/d510mo/devicetree.cb: Indent with tabsArthur Heymans
This is a cosmetic change. Make the formatting consistent with the rest of the tree. Change-Id: Ic90e5584938592f1c2ab41edfcc773702822070d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-01soc/intel/skylake: Clean up SD GPIO handlingAngel Pons
This is to align with newer platforms. Change-Id: If33ea3a7835ec071be3fd060f9712c47678bd6bf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50963 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27mb/intel/shadowmountain: Add the ASL codeV Sowmya
This reverts commit d510b60f5b4eee6c165039be4acbe89ff25d8a4a. This patch includes the DSDT ASL code for shadowmountain board. BUG=b:175808146 TEST= Boot shadowmountain board, dump and verify the DSDT ASL entries. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I5aa60730fc9b93fa97b2bafbb8b2714b6b37becc Reviewed-on: https://review.coreboot.org/c/coreboot/+/50993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-27mb/intel/shadowmountain: Add the ramstage codeV Sowmya
This patch includes the ramstage changes for the shadowmountain board. BUG=b:175808146 TEST= Build and boot shadowmountain board. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I419eecefddf9ee6e4249ada041ebeb1b78e85eb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49732 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27vboot: update GBB flags to use altfw terminologyJoel Kitching
As per CL:2641346, update GBB flag names: GBB_FLAG_FORCE_DEV_BOOT_LEGACY -> GBB_FLAG_FORCE_DEV_BOOT_ALTFW GBB_FLAG_DEFAULT_DEV_BOOT_LEGACY -> GBB_FLAG_DEFAULT_DEV_BOOT_ALTFW BUG=b:179458327 TEST=make clean && make test-abuild BRANCH=none Signed-off-by: Joel Kitching <kitching@google.com> Change-Id: I0ac5c9fde5a175f8844e9006bb18f792923f4f6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-24mb/intel/adlrvp_m: Add initial code for adl-m variant boardVarshit Pandya
List of changes: 1. Add mainboard Kconfig to Kconfig.name files 2. Handle mainboard names in Kconfig file for adlrvp 3. Created a new devicetree.cb for Adlrvp-m. 3. Add override devicetree for ADL-M RVP. 4. Configure proper PCI and USB ports as per schematics for ADL-M BUG=None BRANCH=None TEST=Able to build ADL-M RVP variants adlrvp_m and adlrvp_m_ext_ec. Signed-0ff-by: Maulik Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: I997b89ba87fb03dfa6a836caec51efd05baa2e8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/49871 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22mb/intel/adlrvp: Add support for LP5 SKU with boardid 0x17Subrata Banik
Change-Id: I4f17f9d58d2c07264d7d8e83a6fce832c9304c24 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-22mb/intel/harcuvar: Drop build guards for ENABLE_FSP_MEMORY_DOWNAngel Pons
Ensure the code gets build-tested for CONFIG_ENABLE_FSP_MEMORY_DOWN=n. Change-Id: I6213e3e0ea3b2acfc97017739ac069ee3811d742 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-22mb/intel/shadowmountain: Add the romstage codeV Sowmya
This patch includes the romstage changes for the shadowmountain board. BUG=b:175808146 TEST= Build and boot shadowmountain board till early ramstage. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Ifd0bbcea9d4916d82bb1e3c275dd79d97a79727a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49731 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-17mb: guard irq_tables for clang-formatPatrick Georgi
Some (notably older Intel) boards use a tabular description of irq routing that we want to keep pristine no matter what clang-format considers correct (as that's ugly). Change-Id: I259255a9f60208c659b658ecb81535e84a2aaa8c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-02-17mb/intel/adlrvp: Fix incorrect SPD address issue on DDR4/DDR5Subrata Banik
Assign 7-bit address of the targeted slave SPD. TEST=Able to read correct SPD data from SMBUS. Change-Id: If24e61b583638be7c055541c6eb126da28b542f6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-17mb/intel/adlrvp: Early program SMBUS CLOCK and DATASubrata Banik
TEST=Ensure SMBUS CLK/DATA GPIO is in NF1. Change-Id: Id615462cc21fc24e7ec6ef16274d784d41bd9bd4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-16mb/{intel,prodrive,protectli}: Remove unused <string.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<' Change-Id: Id2aa085a4762355d9fb1628df40f7b43fbc81fc0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-16soc/inteL/broadwell: Move select CHROMEOS_RAMOOPS_DYNAMICKyösti Mälkki
With this selected, chromeos_reserve_ram_oops() is a no-op. Change-Id: I2f3b7b3c4a9549a14f2ba039c769546f9698409a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-15src/mb: Remove unused <console/console.h>Elyes HAOUAS
Change-Id: I6e0f33172fbcecebddfccdf64c22685636a23936 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50524 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15broadwell boards: Switch to Lynxpoint GPIO headersAngel Pons
Move `CROS_GPIO_DEVICE_NAME` to a new `chromeos.h` header, because Lynxpoint uses a different value. Also drop unnecessary includes. Tested with BUILD_TIMELESS=1, Google Tidus remains identical. Change-Id: I38baed2c114fb93cfb82535a6ec00fb67e596d64 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50080 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/intel/wtm2: Switch to Lynxpoint GPIO macrosAngel Pons
Prepare to unify Lynxpoint LP and Broadwell GPIO code. Tested with BUILD_TIMELESS=1, Intel WTM2 remains identical. Change-Id: I422421cc3c336a7a1aceaff7b37ab7c82f64a03f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50067 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15soc/intel/broadwell/pch: Rename GPIO identifiersAngel Pons
Rename structs, types and functions to match Lynx Point's names. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I11ea27b00b5820eb5553712e0420836470ec0d27 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50064 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14ACPI: Move common _PIC methodKyösti Mälkki
Change-Id: I659835354570fb1d4860fcbddf2a51831170a374 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-12haswell boards: Correct USB config indentationAngel Pons
Change-Id: I72b717a41c5611cf578ce178722029b8646cbb35 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50539 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12haswell: Drop `mainboard_fill_pei_data`Angel Pons
Use global variables to provide mainboard USB settings, and have the northbridge code copy it into the `pei_data` struct. For now. To minimize diffstat noise, this patch does not reindent the now-global mainboard USB configuration arrays. This is cleaned up in a follow-up. Change-Id: I273c7a6cd46734ae25b95fc11b5e188d63cac32e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50538 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12mainboard: Drop unneeded `default_brightness_levels.asl`Angel Pons
Desktop boards do not have any backlight control. Change-Id: Ie9f5f4d7e6ae09b3d664d53e4c03157fd4ed088e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-12sandybridge MRC boards: Drop channel disable masksAngel Pons
Platform code will overwrite these values anyway, so do not program them in mainboards. Change-Id: I7571d336a1402c6cfae5835a95dc706a28106271 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49751 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11sb/intel/i82801jx: Drop Global NVS supportAngel Pons
Was copy-pasted from i82801ix and no mainboard actually needs it. Change-Id: I400424540b52dc5d43aba15720b18ad57ea2ebda Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49279 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11ACPI: Move PICM declarationKyösti Mälkki
Variable PICM was not inside GNVS region and can use a static initialisation value. For most AMD platforms PICM default changes from 1 to 0. Fix comments about PICM==0 used to indicate use of i8259 PIC for interrupt delivery. Change-Id: I525ef8353514ec32941c4d0c37cab38aa320cb20 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49905 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11sb,soc/intel: Drop OSYS from GNVSKyösti Mälkki
The value should be set by OSPM using some combination of _OSI() queris in the \_SB._INI() method. To maintain previous behaviour with this commit, boards where GNVS osys initialisation was removed now do the same in ASL. Change-Id: Id4957b12a72fbf7fa988e7ff039e47abcc072e1c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49353 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11mainboards: Drop PWRS from GNVSKyösti Mälkki
Initialize variable to 1 to indicate AC power supply. If platform has EC it will set this correctly based on whether plugged on the charger or not. Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49352 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11src: Remove unused <cpu/intel/model_206ax/model_206ax.h>Elyes HAOUAS
Change-Id: I67862a6a5110e2cab4f77388caa702494e4d71c9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11src: Remove unused <arch/cpu.h>Elyes HAOUAS
Change-Id: I1112aa4635a3cf3ac1c0a0834317983b4e18135a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11Revert "mb/intel/shadowmountain: Add the ASL code"Patrick Georgi
This reverts commit 2151f7561d728a9280d69d20ef56a9fe44db7cb1. Reason for revert: It depends on the shadowmountain ramstage patch. Error on the builder: IASL /cb-build/coreboot.0/default/INTEL_SHADOWMOUNTAIN/dsdt.aml src/mainboard/intel/shadowmountain/dsdt.asl:4:10: fatal error: baseboard/ec.h: No such file or directory #include <baseboard/ec.h> ^~~~~~~~~~~~~~~~ compilation terminated. Change-Id: I9fa5e8cc2ad485bf82bfbda151bc46d26faef7ab Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11mb/intel/shadowmountain: Add the ASL codeV Sowmya
This patch includes the DSDT ASL code for shadowmountain board. BUG=b:175808146 TEST= Boot shadowmountain board, dump and verify the DSDT ASL entries. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I511b2d23c424b0565ad1abcc3b41cace1b89936e Reviewed-on: https://review.coreboot.org/c/coreboot/+/49733 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/intel/wtm2: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are same. Change-Id: Id68623cfb57e889e60d66cd465612336cd8298ca Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-10nb/intel/sandybridge: Use common {DMI,EP,MCH}BAR accessorsAngel Pons
Drop unused sandybridge.h includes to avoid build failures on Ironlake. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: If2f0147fe50266e2fe2098cafdf004e51282f5e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-10mb/intel/adlrvp/bootblock.c: Remove unused includesElyes HAOUAS
Change-Id: I73234da6e77f83c6aeb5c40cf6ffdb3cccc4074c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-06mb/intel/shadowmountain: Add bootblock and verstage codeV Sowmya
This patch includes the bootblock and verstage changes for shadowmountain board. BUG=b:175808146 TEST= Build and boot shadowmountain board till early romstage. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I5f805baf42203306ff10e91a258d9117dd986c4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2021-02-05soc/intel/alderlake: Refactor PCIE port configEric Lai
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b Reviewed-on: https://review.coreboot.org/c/coreboot/+/48340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-04src: Remove unused <cbfs.h>Elyes HAOUAS
Change-Id: Idc11f1e131df2e01864fedac864bda5e11f2d17b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-04mainboards: Remove default CHROMEOS=yKyösti Mälkki
Even the boards with MAINBOARD_HAS_CHROMEOS need to be build-tested with CHROMEOS=n. Change-Id: I16fcf62a23dae1b21c77cee275c867f9c1de893b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-03src: Remove unused <boardid.h>Elyes HAOUAS
Change-Id: I960870fabde1dacfe52a8a35c253b0bd097d3e10 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-02-01soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQSubrata Banik
As per Hardware Architecture Specification (HAS) ADL-P has 7 CLKSRC and 10 CLKREQ (7 SRCCLK is internal and 3 SRCCLK from external CLK chip). ADL-M has 6 SRCCLK and CLKREQ (no external CLK chip). Change-Id: I7d223c165f819669722cbc80245fa8ec20372352 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50130 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30mb/intel/adlrvp: Remove unnecessary whitespaceSubrata Banik
Change-Id: I46af3e789de10ca6951b9e17f286c094c08a477f Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-28mb/intel/adlrvp: Configure SATA DEVSLP as per latest schematicsSubrata Banik
1. GPP_E5 => Remove unused GPIOs 2. GPP_H12, GPP_H13 => Program the correct Native Functions for GPIO Change-Id: I588a8c1153eaa1bf818a081c6c5d18a669017d95 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-28ACPI: Move include for <vc/google/chromeos.asl>Kyösti Mälkki
Change-Id: I4356a8bda71e84afe8c348d366479c5006bf2459 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49796 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/intel/adlrvp: Remove ClkReq assignment for RP8Subrata Banik
CLKSRC6 for RP8 is free-running CLK hence ClkReq is not required. TEST=Able to detect PCIe SD card over x1 slot. Change-Id: I550d5be9cc7566708b0b86fcd1da833bc4bc828f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-28mb/intel/shadowmountain: Add flash layoutV Sowmya
This patch adds the flash layout for shadowmountain. BUG=b:175808146 TEST=util/abuild/abuild -p none -t intel/shadowmountain -a -c max Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I7073d9c783684051e33e7a33eca50007d286bb00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-01-27ACPI: Add top-level ASLKyösti Mälkki
Objects that are created with acpigen need to be declared with External () for the generation of dsdt.asl to pass iasl without errors. There are some objects that are common to all platforms, and some that should be declared only conditionally. Having a top-level ASL helps to achieve this. Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-27ACPI: Separate device_nvs_tKyösti Mälkki
Remove typedef device_nvs_t and move struct device_nvs outside of global_nvs. Also remove padding and the reserve for chromeos_acpi_t. Change-Id: I878746b1f0f9152a27dc58e373d58115e2dff22c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-25soc/intel/adl and mb/intel/adlrvp: Use the newly added meminit block driverFurquan Shaikh
This change uses the newly added meminit block driver and updates ADL SoC and mainboard code accordingly. BUG=b:172978729 Change-Id: Ibcc4ee685cdd70eac99f12a5b5d79fdbaf2b3cf6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-01-25soc/intel/tgl and tgl mb/google,intel: Use the newly added meminit block driverFurquan Shaikh
This change uses the newly added meminit block driver and updates TGL SoC and mainboard code accordingly. TEST=Verified that UPDs are configured correctly with and without this change. Change-Id: I6d58cd6568b7bbe03c4e3011b2301209893e85a9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-24mainboard/intel/strago/ec.c: Use __func__Elyes HAOUAS
Change-Id: Ifa30e9d2a71eae9a438e84367fd8b4f8bd920983 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mainboard/intel/emeraldlake2/ec.c: Use __func__Elyes HAOUAS
Change-Id: I75f534245d37f401357b611efc5c190e8a872d02 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24arch/x86: Use wildcard for mb/smihandler.cKyösti Mälkki
Change-Id: I306f8cd74af62c0cd30f445d20c47f774f122481 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49247 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24broadwell: Flatten `mainboard_pre_raminit`Angel Pons
All Broadwell boards only use the `mainboard_pre_raminit` function to call `mainboard_fill_pei_data` and optionally `mainboard_fill_spd_data`. Move the declaration and weak definition of `mainboard_fill_spd_data` to platform code, replace the call to `mainboard_pre_raminit` in romstage.c with calls to `mainboard_fill_pei_data` and `mainboard_fill_spd_data`, and delete all other instances of `mainboard_pre_raminit` for Broadwell. Finally, delete now-empty romstage.c and spd.h files from mainboards. Change-Id: I3334b20bd7138bb753b996a137ff106e87c6e8a5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24broadwell: Clean up `mainboard_post_raminit`Angel Pons
Make it optional and change its signature. Change-Id: I4b5f3fb08e8954514ebf39e72c95aa62d66856d7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24soc/intel/broadwell: Select CPU_INTEL_HASWELLAngel Pons
This allows us to drop many now-redundant Kconfig options. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. The default configuration file also remains identical, as expected. Change-Id: I20b0200550508679bf2533342ce918b221dcf81e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-24mb/intel/wtm2: Use Haswell CPU codeAngel Pons
Change-Id: I478576afa3b390cf5480298aafe6e049b5e90bff Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46947 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-23mb/intel/coffeelake_rvp: do UART pad configuration at board-levelMichael Niewöhner
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: Ib827e9b2919dbd0e16f30b8dfde46348365d9622 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-21mb/intel/kblrvp: do UART pad configuration at board-levelMichael Niewöhner
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: I8b30eb5d70c34ae3e2ed24ab52dd1357a54c5ae7 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49439 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21mb/intel/minnow3: do UART pad configuration at board-levelMichael Niewöhner
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: I0b956427a9cec56d06b03f7f05138f75137b4ea3 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49437 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21mb/intel/leafhill: do UART pad configuration at board-levelMichael Niewöhner
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: Ibc727302109456eb1d86652c947ce85b3a64c5b2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49436 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21mb/intel/glkrvp: do UART pad configuration at board-levelMichael Niewöhner
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: I80369ab70d5510cb4f388f3029119e7148361af4 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49435 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21mb/intel/apollolake_rvp: do UART pad configuration at board-levelMichael Niewöhner
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to a early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: Id6b55d7f3d3fbfc5b55497708f24006614760d03 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49434 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 16:19:40 +0000