| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-11-12 | soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to devicetree | Arthur Heymans |
| 2021-01-24 | mb/intel/wtm2: Use Haswell CPU code | Angel Pons |
| 2020-10-30 | soc/intel/broadwell: Separate PCH in devicetree | Angel Pons |
| 2020-10-30 | mb/intel/wtm2: Prepare devicetree for PCH split | Angel Pons |
| 2020-07-28 | broadwell: Factor out PIRQ routing from devicetree | Angel Pons |
| 2020-07-26 | mb/*/*/devicetree.cb: Normalize disabled PIRQ values | Angel Pons |
| 2020-01-10 | mb/intel/wtm2/devicetree.cb: Align comments | Angel Pons |
| 2015-01-04 | wtm2: Convert to use soc/intel/broadwell | Duncan Laurie |
| 2013-11-25 | wtm2: Set SerialIO I2C ports to 3.3V | Duncan Laurie |
| 2013-11-24 | haswell: configure c-states | Aaron Durbin |
| 2013-04-01 | wtm2: Enable SerialIO devices in ACPI mode | Duncan Laurie |
| 2013-03-21 | haswell/lynxpoint: Use new PCH/PM helper functions | Duncan Laurie |
| 2013-03-18 | Add Intel Whitetip Mountain 2 mainboard | Duncan Laurie |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |