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In order to create a working baseline all ports are being set to have
retimers. Setting the TcssAuxOri UPD to 0 in order for the SoC to not
misconfigure the ports. Volteer will need some additional changes after
this is implemented to account for ports that do not have a retimer.
This setting is in the process of being documented in the TGL EDS and we
can update once it is fully understood what this setting is changing on
the SOC side.
BUG=b:145943811
BRANCH=none
TEST=Boot to OS and check Type-C port1 Display on Volteer,
Connecting Type-c display should work regardless of Type-c cable
orientation.
Change-Id: I29eb0513299126ad8d1ee11ded2c771f28ad13f3
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39460
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update the GPE configuration for dw0, dw1 and dw2.
BUG=None
TEST=build and boot tglrvp
Change-Id: I8b406bcbd710e84cec91a8c2d1557902e929f7cc
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39844
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update Audio AIC UPD settings and gpio pad configs for Tiger Lake.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I45935b79f6fa4ad66238eead9258a4f15feec508
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I426518e8e18de1c8efcfb7ecb0835df3e257dca1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39608
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BRANCH=none
BUG=b:145946347
TEST=boot to OS with TGL RVP UP3,
then copied ISH firmware to host file system /lib/firmware/intel/tglrvp_ish.bin
check "dmesg |grep ish", it shows:
ish-loader: ISH firmware intel/tglrvp_ish.bin loaded
cros_ec_ishtp: Chrome EC device registered
Those means shim loader in coreboot has loaded ISH firmware, and
firmware is running successfully.
Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Signed-off-by: li feng <li1.feng@intel.com>
Change-Id: I1ee8050aef6ec0828f16ef2695b5347278caa820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39481
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update GPIO reset type from PLTRST to DEEP.
DEEP setting is more conservative for S3/S4/S5.
Detail information is bug.
BUG=b:151305120
TEST=Build and boot to OS
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ie7d08560ea2ef3623bbd4734b30c80e707869c7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39476
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP form NVMe and Optane
Check PCIe lane configuration
Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I5fc8fa0897ad006de9ebe20115bf3033e1e1b499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
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During intial UP4 patch, below UP3 patches merged which should be
applied for UP4.
https://review.coreboot.org/c/coreboot/+/39201
https://review.coreboot.org/c/coreboot/+/39229
Merge these patches to UP4
BUG=none
BRANCH=none
TEST=Build TGL UP4
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I7b24cb2b0d03309cf67c6c21ddc2031a054f6110
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
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This change uses drivers/intel/wifi chip for CNVi device and
adds dynamic SSDT entires for CNVi also export wake gpio for CNVi
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board and check for SSDT entries
for CNVi
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Icdbffa0c29c9e0849a6a99f8592b6f35c0bb3207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39315
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add LPDDR4 memory configuration for Tiger Lake UP4 platform which
includes
1. DQ/DQs Mapping
2. Board id Support
3. SPD indexing
BUG=none
BRANCH=none
TEST= Build TGL UP4 successfully
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ibbd7036919c1a91ef12049d2af657f0a3597b57e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39365
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add initial TGL UP4 RVP build enviorment
BUG=none
BRANCH=none
TEST= Build TGL UP4 successfully
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Iab7ada0746394539586e7cc159112dc8208fdd7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39363
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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