coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-01-25	soc/intel/tgl and tgl mb/google,intel: Use the newly added meminit block driver	Furquan Shaikh
2020-06-02	src: Remove unused '#include <cbfs.h>'	Elyes HAOUAS
2020-05-18	src: Remove unused 'include <string.h>'	Elyes HAOUAS
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-06	mainboard/intel: Use SPDX for GPL-2.0-only files	Angel Pons
2020-04-02	soc/intel/tigerlake: Reorganize memory initialization support	Furquan Shaikh
2020-04-01	soc/intel/tigerlake: Remove Jasper Lake SoC references	Aamir Bohra
2020-03-18	mainboard/[g-p]*: Remove copyright notices	Patrick Georgi
2020-03-09	mb/intel/tglrvp: Add memory config for Tiger Lake UP4	Srinidhi N Kaushik
2020-02-26	mb/intel/tglrvp: add Tiger Lake memory initialization support	Srinidhi N Kaushik
2020-01-14	mb/intel/tglrvp: Add initial mainboard code	Ravi Sarawadi