| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-03-09 | mb/intel/tglrvp: Add memory config for Tiger Lake UP4 | Srinidhi N Kaushik |
| 2020-02-26 | mb/intel/tglrvp: add Tiger Lake memory initialization support | Srinidhi N Kaushik |
| 2020-01-14 | mb/intel/tglrvp: Add initial mainboard code | Ravi Sarawadi |
 |
index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |