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2023-02-19treewide: Remove useless "_STA: Status" commentElyes Haouas
Change-Id: I99ded00fa6dadb494c1523d00063dbc1fde95614 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73093 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-17treewide: Remove unuseful "_UID: Unique ID" commentElyes Haouas
Change-Id: I150a4ed94bcaead6eb45f1c4b4952ae6957e0940 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_HID: Hardware ID" commentElyes Haouas
Change-Id: I5eb1424e9e6c1fbf20cd0bf68fbb52e1ec97f905 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-27mainboard/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I4f2f02623b060ef0ebefc5aceb713c77a8b1e9a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71523 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-27mainboard/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: Id1078b14a805eea53d2a7c5a8183a5413f26e115 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71521 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-13mb/intel/latest mainboards: Get rid of power button device in corebootSubrata Banik
Refer to commit d7b88dc (mb/google/x86-boards: Get rid of power button device in coreboot) This change gets rid of the generic hardware power button from all intel mainboards and relies completely on the fixed hardware power button. Change-Id: I8f9d73048041d42d809750fdb52092f40ab8f11f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-12mb/intel: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated buils/dsdt.dsl for intel/kblrvp11 are same. Change-Id: I41195be171b48f41fe2955e4639d8b770853d483 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10src/mb: Remove unneeded spaces before/after tabsElyes HAOUAS
Change-Id: I02979a0632a7b356985f96c3ba239daba178b4e3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39989 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06mainboard/intel: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I1ea2eebfdd43610e42b4cf04409ec76c2e8b0042 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40082 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23src/mb/intel/tglrvp: Fix board config flag for TGL-UP4 camera ACPIDaniel Kang
Camera ACPI had an incorrect board config flag for TGL-UP4. BUG=None BRANCH=None TEST=Build and boot TGLRVP-UP3 or UP4. Start camera app and able to capture images. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: Ided0e146a9240169d3f1f27a86218ac1a942b899 Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-18mainboard/[g-p]*: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I426518e8e18de1c8efcfb7ecb0835df3e257dca1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39608 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-17src/mb/intel/tglrvp: Update camera ACPI configurationDaniel Kang
* Change power sequence to make it closer to ov8856 sensor data sheet version 2 * Handle different PWREN GPIO pins for up3 and up4 * Add link frequencies definitions to sensor side * Clean up format BUG=None BRANCH=None TEST=Build and boot TGLRVP U or Y. Start camera app and able to capture images. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: Ic11a36f1f82fe425c1a5796847ce020007064403 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39529 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-17src/soc/intel/tigerlake: Fix incorrect use of Field objects in ASLRizwan Qureshi
Method RAOW is assuming that the first argument is a Field object and writing to it expecting the register to get updated. However, the callers are passing in the value of the Field object instead. This eventually is resulting the IMGCLK not getting enable/disabled on the platform. Fix this by sending the exact address of the register to be updated. Also MCCT was setting the clock frequency in both case i.e, Clock Enable and Disable. Split the MCCT method in two, MCON and MCOF to fix the sequencing like below MCON: Set frequency Enable clock MCOF: Disable clock Also, make use of MCON and MCOF methods for camera clock control in tglrvp. This is to avoid the buildbot marking the patch unstable. BUG=None BRANCH=None TEST=Build and Boot waddledoo board and verified that IMGCLKOUT for world facing camera is enabled/disabled and able to capture images. Build and Boot Tiger Lake RVP board and verified that IMGCLKOUT for world facing camera is enabled/disabled and able to capture images. Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: I8b886255d5f38819502ae1f4af0851b5a0922b22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39498 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-27mb/intel/tglrvp: Enable MIPI cameraWonkyu Kim
Add MIPI camera ACPI Update GPIO pin mux for camera BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check camera Simple test method to check camera: capture image by below commands from OS console >media-ctl -V "\"Intel IPU6 CSI-2 5\":0 [fmt:SGRBG10/3280x2464]" >media-ctl -V "\"Intel IPU6 CSI-2 5\":1 [fmt:SGRBG10/3280x2464]" >media-ctl -l "\"ov8856 18-0010\":0 -> \"Intel IPU6 CSI-2 5\":0[1]" >media-ctl -V "\"Intel IPU6 CSI2 BE\":0 [fmt:SGRBG10/3280x2464]" >media-ctl -V "\"Intel IPU6 CSI2 BE\":1 [crop:(0,0)/3280x2464]" >media-ctl -V "\"Intel IPU6 CSI2 BE\":1 [fmt:SGRBG10/3280x2464]" >media-ctl -l "\"Intel IPU6 CSI-2 5\":1 -> \"Intel IPU6 CSI2 BE\":0[1]" >media-ctl -l "\"Intel IPU6 CSI2 BE\":1 -> \"Intel IPU6 CSI2 BE capture\":0[1]" >yavta -u -c5 -n5 -I -s 3280x2464 --file=/tmp/frame-#.bin -f SGRBG10 $(media-ctl -e "Intel IPU6 CSI2 BE capture") Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I4189e96f68f0e64e0860405e00eeab84564b86be Reviewed-on: https://review.coreboot.org/c/coreboot/+/37863 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14mb/intel/tglrvp: Add initial mainboard codeRavi Sarawadi
This is a initial mainboard code aimed to serve as base for further mainboard check-ins. This is a copy patch from icelake_rvp as on commit ID: I64db2460115f5fb35ca197b83440f8ee47470761 Below are the changes done over the copy patch: 1. Rename "Icelake" with "Tigerlake". 2. Replace "icelake_rvp" with "tglrvp". 3. Rename "icl" with "tgl". 4. Remove unwanted SPD file, add empty SPD as placeholder. 5. Replace "soc/intel/icelake" with "soc/intel/tigerlake". 6. Empty romstage_fsp_params.c, to fill it later with SOC specific config. 7. Empty GPIO configuration, to be filled as per board. 8. Change copyright year to 2019. 9. Add board support namely BOARD_INTEL_TGLRVP_UP3 10. Replace icl_u and icl_y variant with tglrvp variant. 11. Remove basebord gpio.c and rely on variant override. 12. Remove HDA verb table and config support. Changes to follow on top of this: 1. Add correct memory parameters, add SPDs. 2. Clean up devicetree as per tigerlake SOC. 3. Add GPIO support. 4. Update chromeos.fmd to make 32MB BIOS region. 5. clean up and make empty devicetree setting TEST=Build tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I86ada611de1cf28a1b872eea35cf41c0dc1c57f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-18 12:08:00 +0000