coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-03-28	mb/intel/shadowwmountain: Enable CSE Lite SKU for shadowmountain	Sridhar Siricilla
2021-03-26	mb/intel/shadowmountain: Disable the unused CPU PCIe RP	V Sowmya
2021-03-17	mb/intel/shadowmountain: Update HDMI audio mode to 8T	Sugnan Prabhu S
2021-03-17	mb/intel/shadowmountain: Disable xDCI	Sugnan Prabhu S
2021-03-15	mb/intel/shadowmountain: Add ACPI entry for BT reset GPIO	Aamir Bohra
2021-03-12	mb/intel/shadowmountain: Enable Type-C subsystem	V Sowmya
2021-02-27	mb/intel/shadowmountain: Add the ASL code	V Sowmya
2021-02-27	mb/intel/shadowmountain: Add the ramstage code	V Sowmya
2021-02-27	vboot: update GBB flags to use altfw terminology	Joel Kitching
2021-02-22	mb/intel/shadowmountain: Add the romstage code	V Sowmya
2021-02-11	Revert "mb/intel/shadowmountain: Add the ASL code"	Patrick Georgi
2021-02-11	mb/intel/shadowmountain: Add the ASL code	V Sowmya
2021-02-06	mb/intel/shadowmountain: Add bootblock and verstage code	V Sowmya
2021-01-28	mb/intel/shadowmountain: Add flash layout	V Sowmya
2021-01-27	ACPI: Add top-level ASL	Kyösti Mälkki
2020-12-21	mb/intel/shadowmountain: Add Intel Pre-CEP shadowmountain board	V Sowmya