| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-04-21 | mb/intel/shadowmountain: Disable GSPI1 interface connected to FPS | Sridhar Siricilla |
| 2021-04-10 | mb/intel/shadowmountain: Enable Bluetooth config in the devicetree | Sridhar Siricilla |
| 2021-04-06 | mb/intel/shadowmountain: Add Cr50 support | Aamir Bohra |
| 2021-03-26 | mb/intel/shadowmountain: Disable the unused CPU PCIe RP | V Sowmya |
| 2021-03-17 | mb/intel/shadowmountain: Update HDMI audio mode to 8T | Sugnan Prabhu S |
| 2021-03-17 | mb/intel/shadowmountain: Disable xDCI | Sugnan Prabhu S |
| 2021-03-15 | mb/intel/shadowmountain: Add ACPI entry for BT reset GPIO | Aamir Bohra |
| 2021-03-12 | mb/intel/shadowmountain: Enable Type-C subsystem | V Sowmya |
| 2021-02-27 | mb/intel/shadowmountain: Add the ramstage code | V Sowmya |
| 2021-02-22 | mb/intel/shadowmountain: Add the romstage code | V Sowmya |
| 2021-02-06 | mb/intel/shadowmountain: Add bootblock and verstage code | V Sowmya |
| 2020-12-21 | mb/intel/shadowmountain: Add Intel Pre-CEP shadowmountain board | V Sowmya |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |