| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-10-26 | mb/intel/saddlebrook: migrate to FSP 2.0 | Michael Niewöhner | |
| This patch is part of the patch series to drop support for FSP 1.1 in soc/intel/skylake. The following modifications have been done to migrate the board(s) from FSP 1.1 to FSP 2.0: - remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0) TODO: - testing Change-Id: I7481f3413de6780df01d9b769bd4f16d439f087c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35923 Reviewed-by: Michael Niewöhner Reviewed-by: Wim Vervoorn Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> | |||
| 2017-12-19 | mainboard/intel/saddlebrook: add support for Saddle Brook | Teo Boon Tiong | |
| Add initial files to support the Saddle Brook board. This board uses the Skylake FSP 1.1 image and does not build without the FspUpdVpd.h file. Most of the code has been taken carried over from kunimitsu with changes done for Saddle Brook. Saddle Brook is a reference board for Skylake SOC and has DDR4. TEST=Build with uefi payload and boot to Linux 4.9 on CRB successfully. Change-Id: Ie221eb58e8ab8ff15e9ef19c1d145a5eb2921b4e Signed-off-by: Anuj Mittal <anujx.mittal@intel.com> Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/21436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> | |||
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