| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-05-07 | mb/intel/saddlebrook: Refactor to get rid of `pei_data` | Nico Huber | |
| The SoC specific `struct pei_data` was filled with values that were later only consumed by the mainboard code again. Avoid jumping through this hoop and fill FSP UPDs directly. Change-Id: I399dd89f85ccea43fdf90bd895e71324f4b409cc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> | |||
| 2017-12-19 | mainboard/intel/saddlebrook: add support for Saddle Brook | Teo Boon Tiong | |
| Add initial files to support the Saddle Brook board. This board uses the Skylake FSP 1.1 image and does not build without the FspUpdVpd.h file. Most of the code has been taken carried over from kunimitsu with changes done for Saddle Brook. Saddle Brook is a reference board for Skylake SOC and has DDR4. TEST=Build with uefi payload and boot to Linux 4.9 on CRB successfully. Change-Id: Ie221eb58e8ab8ff15e9ef19c1d145a5eb2921b4e Signed-off-by: Anuj Mittal <anujx.mittal@intel.com> Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/21436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> | |||
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