coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2024-01-24	mb/hp to mb/kontron: Rename Makefiles from .inc to .mk	Martin Roth
	The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Icfdadfa6705a64655b38aca25be0818ec26429f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80110 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-30	mb/intel/mtlrvp: Add romstage and configure LP5 memory parts	Ashish Kumar Mishra
	This patch adds initial romstage code and spd data for LP5 memory parts for MTL-RVP. This also configures memory based on the board id. Memory - x32 LPDDR5 Vendor/Model - Micron/MT62F2G32D8DR-031 WT:B Board ID - 0b0000 - Empty spd hex file 0b0001 - DDR5 (Empty spd hex file) 0b0010 - LPDDR5 (MT62F2G32D8DR-031 WT:B) BUG=b:224325352 TEST=Able to boot intel/mtlrvp (LP5 SKU) to ChromeOS Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Change-Id: I15b352eb246aed23da273e56490c7094eae9d176 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>