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path: root/src/mainboard/intel/mtlrvp/Kconfig
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2023-02-15mb/intel/mtlrvp: Enable mipi_camera for MTL-P RVPUsha P
Add support for MTL-P RVP mipi camera functionality BUG=None TEST=Build and boot MTL-P RVP to Chrome OS. Verify SSDT entries related to mipi camera and verify camera working. Scope (\_SB.PCI0.I2C1) { Device (CAM0) Scope (\_SB.PCI0.I2C0) { Device (CAM1) Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I698edd7155fc38477f3416900799e61d3295fd1a Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Harsha B R <harsha.b.r@intel.com>
2023-02-15mb/intel/mtlrvp: Enable Audio for MTL-P RVPUsha P
This patch adds FW_CONFIG and codec support for MTL-P RVP BUG=None TEST=Build and boot MTL-P RVP to Chrome OS. Verify audio codec listed under aplay -l and audio working with the connected audio card. localhost ~ # aplay -l **** List of PLAYBACK Hardware Devices **** card 0: sofrt5682 [sof-rt5682], device 0: Headset (*) []   Subdevices: 1/1   Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 1: Speakers (*) []   Subdevices: 1/1   Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 5: HDMI1 (*) []   Subdevices: 1/1   Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 6: HDMI2 (*) []   Subdevices: 1/1   Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 7: HDMI3 (*) []   Subdevices: 1/1   Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 8: HDMI4 (*) []   Subdevices: 1/1   Subdevice #0: subdevice #0 Signed-off-by: Usha P <usha.p@intel.com> Change-Id: Ib29ac3e4105e578e1555076d180b35a8265a99c8 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-10mb/intel/mtlrvp: Enable DPTF functionality for mtlrvp boardSumeet Pawnikar
Enable DPTF functionality for Meteor Lake based mtlrvp board BRANCH=None BUG=None TEST=Built and booted on mtlrvp board Change-Id: I8d3e1cd43cf67c3f2081be339589a6da358b668c Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-08mb/intel/mtlrvp: Add ACPI configuration for USB2/3 portsHarsha B R
This patch adds ACPI configuration for USB2/3 ports for mtlrvp as per schematics. This helps in generating corresponding ACPI code at runtime that includes port information. BUG=b:224325352 BRANCH=None TEST=Able to build and boot MTLRVP. Connect USB device and check if corresponding enumeration of USB device (14.0) is observed on executing lspci. 00:14.0 USB controller: Intel Corporation Device 7e7d (rev 01) 00:14.1 USB controller: Intel Corporation Device 7e7e (rev 01) Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ie150247661322e3944be15dc70f66033266d8aac Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72787 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08mb/intel/mtlrvp: Describe mainboard configuration for BB RetimerHarsha B R
This patch describes BB retimer for tcss_dma0 and tcss_dma1 with respect to GPP_B21 as per schematics. +--------------+------------+ | tbt_pcie_rp0 | tcss_dma0 | +--------------+------------+ | tbt_pcie_rp1 | tcss_dma0 | +--------------+------------+ | tbt_pcie_rp2 | tcss_dma1 | +--------------+------------+ | tbt_pcie_rp3 | tcss_dma1 | +--------------+------------+ BUG=b:224325352 BRANCH=None TEST=Able to build and boot MTLRVP to ChromeOS. Verify the enumeration of tbt_pcie_rp as part of lspci. 00:07.0 PCI bridge: Intel Corporation Device 7ec4 00:07.1 PCI bridge: Intel Corporation Device 7ec5 00:07.2 PCI bridge: Intel Corporation Device 7ec6 00:07.3 PCI bridge: Intel Corporation Device 7ec7 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ie1a0026b064aa4f7fcd27e75c0b0d052ec620dcc Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72786 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08mb/intel/mtlrvp: Enable WWAN ACPIHarsha B R
This patch enables FM350GL 5G WWAN support for mtlrvp. BUG=b:224325352 BRANCH=None TEST=Build and boot mtlrvp to ChromeOS. Ensure that WWAN module 00:1c.6 is enumerated as part of lspci and cbmem -c in AP console. Also verify generation of PXSX Device as part of SSDT. Able to connect WiFi and access internet. cbmem -c: \_SB.PCI0.RP07: Enable RTD3 for PCI: 00:1c.6 (Intel PCIe Runtime D3) \_SB.PCI0.RP07: Enable WWAN for PCI: 00:1c.6 (Fibocom FM-350-GL) SSDT: Scope (\_SB.PCI0.RP07) { Device (PXSX) Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I870cc0782fb989f1bdbe369a4a12630a62729d8e Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72779 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-02-07mb/intel/mtlrvp: Enable EC_GOOGLE_CHROMEEC_SWITCHESHarsha B R
This patch enables EC_GOOGLE_CHROMEEC_SWITCHES for MTL_CHROME_EC which helps in mode switch using dut-control power_state:rec. BUG=b:224325352 BRANCH=None Test=Able to build and boot MTLRVP to ChromeOS. Check if chroot command dut-control power_state:rec puts the DUT to recovery mode. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I5de0cd6c9a50bd85238205e09976a8bd8dd7142f Reviewed-on: https://review.coreboot.org/c/coreboot/+/72813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-02-07mb/intel/mtlrvp: Enable ACPI support for Type-C portsHarsha B R
This patch adds ACPI support for Type-C ports. BUG=b:224325352 BRANCH=None Test=Able to build and boot MTLRVP. Verify SSDT for the corresponding entry, \_SB.PCI0.PMC.MUX.CON0 under Device (CON0) \_SB.PCI0.PMC.MUX.CON1 under Device (CON1) \_SB.PCI0.PMC.MUX.CON2 under Device (CON2) \_SB.PCI0.PMC.MUX.CON3 under Device (CON3) Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I8e5957ca7a6c542a64d79b2ceefbed79ead15811 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72789 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-30mb/intel/mtlrvp: Add romstage and configure LP5 memory partsAshish Kumar Mishra
This patch adds initial romstage code and spd data for LP5 memory parts for MTL-RVP. This also configures memory based on the board id. Memory - x32 LPDDR5 Vendor/Model - Micron/MT62F2G32D8DR-031 WT:B Board ID - 0b0000 - Empty spd hex file 0b0001 - DDR5 (Empty spd hex file) 0b0010 - LPDDR5 (MT62F2G32D8DR-031 WT:B) BUG=b:224325352 TEST=Able to boot intel/mtlrvp (LP5 SKU) to ChromeOS Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Change-Id: I15b352eb246aed23da273e56490c7094eae9d176 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-04mb/intel/mtlrvp: Enable CSE Lite SKU for MTL-RVPHarsha B R
This patch will enable Kconfig SOC_INTEL_CSE_LITE_SKU option required to enable CSE-Lite SKU for MTL-RVP. On enabling the respective Kconfig option, CSE reboots the system into CSE_RW FW region on cold reboot. BUG=b:224325352 TEST=Able to boot intel/mtlrvp to ChromeOS and also able to observe CSE boot to RW FW region as part of coreboot console log, localhost ~ # cbmem -c | grep cse [DEBUG] cse_lite: Number of partitions = 3 [DEBUG] cse_lite: Current partition = RW [DEBUG] cse_lite: Next partition = RW Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I325405cc304d245871396317c11ac7a5b062a5bd Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71638 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-29mb/intel/mtlrvp: Add configuration for UART devicesHarsha B R
This patch adds below configuration for MTL-RVP UART devices, Interface -> UART0 PCI -> 0:0x1e:0 Device -> AP UART BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp ito chromeOS using subsequent patches in the train. UART logs appear on AP console. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I4702d603aa49357f4db0d18d646e536d9d81787e Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70873 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-21mb/intel/mtlrvp: Enable ChromeOS build for mtlrvpHarsha B R
This patch enables building ChromeOS for mtlrvp. Patch includes, 1. Add cros_gpios for mtlrvp 2. Add chrome OS configuration in Kconfig 3. Add Chromeos.c BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform with the subsequent patches in the train (CB: 69886) Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ia428941bd8269714c3edca6c7b0c2a3fbf08bd75 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70724 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20mb/intel/mtlrvp: Enable EC for mtlrvpJamie Ryu
This patch will initialize EC for mtlrvp which includes, 1. Add configuration (& choice) for CHROME_EC and INTEL_EC (WINDOWS_EC) 2. Add respective ACPI configuration 3. Add ec.c required for ramstage 4. Program EC ranges as part of devicetree.cb 5. Enable VBOOT in Kconfig BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform with CHROME_EC using subsequent patches in the train Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I662d7f79050d35e152d97dc5c2118a4af56223bc Signed-off-by: Harsha B R <harsha.b.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66101 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09mb/intel/mtlrvp: Add initial code for mtlrvp_p_ext_ec variant boardHarsha B R
This patch adds the initial code for mtlrvp_p_ext_ec variant board which includes 1. support for 2 mainboards (Chrome EC and Windows EC) by adding overridetree.cb to corresponding directory 2. Move devicetree to baseboard/mtlrvp_p 3. Update mainboard name in Kconfig and Kconfig.name 4. Add config option to select corresponding overridetree.cb Subsequent patches include patch train starting from (CB - 66102) BUG=b:260654043 TEST=Able to build with the patch and boot the mtlrvp platform with the subsequent patches Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I83948aa5e9fcaadee4745e313360773c48142f89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com>
2022-11-27mb/intel/mtlrvp: Create baseboard structure for mtlrvpHarsha B R
This patch will create the baseboard structure for mtlrvp. Changes include, 1. Adding Baseboard config for mtlrvp in Kconfig 2. Move gpio.h to corresponding baseboard directory 3. Append header reference to CPPFLAGS_common in Makefile.inc BUG=none TEST=FW_NAME=mtlrvp_p emerge-rex coreboot chromeos-bootimage Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I82acb6879fecb242014258f2c358804d5abbbd48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69971 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-08mb/intel/mtlrvp: Enable ACPI and add ACPI tableJamie Ryu
This enables ACPI configuration and add ACPI table. BUG=b:224325352 TEST=util/abuild/abuild -p none -t intel/mtlrvp -a -c max Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I8264197fd0acdd7e19b9a36fb22822447b013202 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66100 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-07mb/intel/mtlrvp: Add MTL reference mainboard for MTLRVP-PJamie Ryu
This adds an initial mainboard code for mtlrvp, Intel Meteorlake reference platform. BUG=b:224325352 TEST=util/abuild/abuild -p none -t intel/mtlrvp -a -c max Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I097db4de9734ff81283cf470aabf3eb23b63aab8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66097 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 15:53:41 +0000