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2019-11-21mb/*/*: Drop Intel Rangeley mainboardsArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: Id38eada2d08426520261d4824990a49f8302976b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-11-04mb/*/*/others: Use sb/intel/common/acpi/platform.aslArthur Heymans
Change-Id: Iabfd680fdb50534e6b9f6cfdecda9f8de0f8a610 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-01soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpiSubrata Banik
This patch creates a common instance of sleepstates.asl inside intel common code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to refer sleepstates.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify S0/S3/S4/S5 entries after booting to OS. Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-12src: Drop unused 'include <arch/acpigen.h>'Elyes HAOUAS
Use <arch/acpi.h> when appropriate. Change-Id: I05a28d2c15565c21407101e611ee1984c5411ff0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-04device/mmio.h: Add include file for MMIO opsKyösti Mälkki
MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-02-07src: Remove unused include device/pnp_def.hElyes HAOUAS
Change-Id: Ibb7ce42588510dc5ffb04c950c4c8c64e9a2fa37 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-24cpu/intel/model_406dx: Remove the notion of CPU socketsArthur Heymans
Change-Id: I5e8fb2e7331d02224a4199c4d05f92c603c57f78 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31032 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19mainboard: Remove useless include <device/pci_ids.h>Elyes HAOUAS
Change-Id: I4ee3cc42302c44dc80ae1f285579a4d1775aec16 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-30cpu/intel/common: Use a common acpi/cpu.asl fileArthur Heymans
Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: David Guckian
2018-11-28mb/*/*/Kconfig: Remove useless commentElyes HAOUAS
Change-Id: Ibdff50761a205d936b0ebe067f418be0a2051798 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hellsenberg <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-23mb: Set coreboot as DSDT's manufacturer model IDElyes HAOUAS
Field 'OEMID' & "OEM Table ID" are related to DSDT table not to mainboard. So use macro to set them respectvely to "COREv4" and "COREBOOT". Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian
2018-11-21ACPI: Fix DSDT's revision fieldElyes HAOUAS
DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version. This will cause the AML interpreter to use 32-bit integers and math if the version is 1, and 64-bit if the version is >=2. Current spec version is 2 for ACPI 6.2-a. Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29626 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-05mainboard: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: Ib3aafcc586b1631a75f214cfd19706108ad8ca93 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29285 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-17mb/*/*: Clean up FADT checksum assignmentJonathan Neuschäfer
The assignment of header->checksum was in some cases done twice, or unnecessarily split into two lines. Change-Id: Ib0c0890d7589e6a24b11e9bda10e6969c7d73c56 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-08-13mb: Get rid of unneeded include <cbmem.h>Elyes HAOUAS
Change-Id: I80dd65484fd52e9048635091fb20a123e959e999 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27869 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04mb/intel: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I891b056b64fde27ef0e351f8cf24a258fb5cabfa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-31cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDENico Huber
As far as I can see this Kconfig option was used wrong ever since it was added. According to the commit message of 107f72e (Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR), it was only necessary to prevent overlapping with CAR. Let's handle the potential overlap in C macros instead and get rid of that option. Currently, it was only used by most FSP1.0 boards, and only because the `fsp1_0/Kconfig` set it to CBFS_SIZE (WTF?). Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-26mb/*/*/cmos.layout: Fix the values for the console levelArthur Heymans
Fix the values that were off by one. This was discovered when using postcar stage that prints with debuglevel BIOS_NEVER. Change-Id: I73a077950ed0dc735d89c9747a8da0a25f30822d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-26mainboard: use SeaBIOS config only when it's the payload of choiceLubomir Rintel
It makes no sense for Das U-Boot which uses the same setting. Change-Id: I1629aecf33cb62bb1e6856ef5627748a7dc74d8a Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/21611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-23mb/*/*: Remove rtc nvram configurable baud rateArthur Heymans
There have been discussions about removing this since it does not seem to be used much and only creates troubles for boards without defaults, not to mention that it was configurable on many boards that do not even feature uart. It is still possible to configure the baudrate through the Kconfig option. Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-06-06mb/*/*/cmos.layout: Make multibyte options byte alignedArthur Heymans
Changes the offsets of some options so that options that span multiple bytes are byte aligned. To make the cmos.layout file more consistent some things where moved around in the cmos.layout of thinkpads X200 and T400. Change-Id: Ic84a2a5dc6f9c102f041085871c2ed55e2f3692a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-03-21mainboards: Don’t select `POST_IO`Paul Menzel
Currently, it’s impossible for the user to select `NO_POST`, for boards selecting it in their config. ``` warning: (BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS) selects POST_IO which has unmet direct dependencies (VENDOR_ASUS && (BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO || BOARD_ASUS_F2A85_M_LE) && (BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO) || VENDOR_MSI && BOARD_MSI_MS7721 || PC80_SYSTEM && !NO_POST) ``` This is currently done for Intel Mohon Peak, and its descendants. Selecting the option `POST_IO` in board specific configuration is not a good idea, as this should be user configurable over Kconfig, and also the tree-wide defaults should be the same for these options. Change-Id: Ia4ab0d942b7d66f18466a770ef739109ab0db629 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18877 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-06cpu/x86/msr.h: Drop excessive includesKyösti Mälkki
Change-Id: Ic22beaa47476d8c600e4081fc5ad7bc171e0f903 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17735 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22Remove explicit select MMCONF_SUPPORTKyösti Mälkki
Make MMCONF_SUPPORT selected with MMCONF_SUPPORT_DEFAULT. Platforms that remain to have explicit MMCONF_SUPPORT are ones that should be converted. Change-Id: Iba8824f46842607fb1508aa7d057f8cbf1cd6397 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17527 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-20src/mainboard/getac - kontron: Add space around operatorsElyes HAOUAS
Change-Id: If3cdfdff60c92e3427f1b285e2bca92e2bb2a1cb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16640 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-17mainboard: Clean up boot_option/reboot_bits in cmos.layoutNico Huber
Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector code) the reboot counter stored in `reboot_bits` isn't reset on a reboot with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR enabled, later stages (e.g. payload, OS) have to clear the counter too, when they want to switch to normal boot. So change the bits to (h)ex instead of (r)eserved. To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also remove all occurences of the obsolete `last_boot` bit that have sneaked in again since 24391321 (mainboard: Remove last_boot NVRAM option). Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/16157 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-12-09mohonpeak/Kconfig: Fix whitespace issuesMartin Roth
Auto-indent did me wrong, and I didn't notice it. Change-Id: I5a736cf53a3bdbe57b28b2d6a55befd341d8dfd8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12655 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-12-06intel/fsp_rangeley: change non-existent config options to #definesMartin Roth
Kconfig symbols CONFIG_ACPI_INCLUDE_PMIO and CONFIG_ACPI_INCLUDE_GPIO were never added to the coreboot codebase when the Rangeley code was brought in from Sage. These symbols disabled ACPI code that was unused because it caused dmesg warnings due to conflicts with drivers trying to claim the same addresses as the ACPI code. Because it could be used on some other platforms, it was left in instead of being completely removed. - Change the Kconfig symbol names to simple #defines in the mainboard code. - Add the #defines along with comments to the reference platform. - Hook everything together in dsdt.asl - Update new mainboard littleplains the same way. Change-Id: I1f62157c6e447ea9b7207699572930e4711fc3e0 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12552 Reviewed-by: David Guckian <david.guckian@intel.com> Tested-by: build bot (Jenkins)
2015-12-06Rangeley: Change A, A, A, A INT routing to A, A, A, BMartin Roth
Devices that have their interrupt routing set to A, A, A, A don't get any interrupt values assigned because that series evaluates to 0. The code that sets the interrupt values checks to make sure a value is set by verifying that it's not 0. On Bay Trail, these are all single-function graphics devices, so by changing one of the unused interrupt lines from A to any other value, it assigns the values correctly. This issue did not affect ACPI interrupt routing. This is just a workaround, and the root issue still needs to be fixed. Change-Id: I4e6fe56084cbe86b309da15d61b296f1936458ec Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12630 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03intel/mohonpeak: Change SEABIOS_MALLOC_UPPERMEMORY to config_seabiosMartin Roth
Instead of the SEABIOS_MALLOC_UPPERMEMORY option, use a saved SeaBIOS .config file to do the same thing. Change-Id: I29110a382b7770329ef938876426e571fbbbb339 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12569 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-11-10mainboard: Remove empty mainboard.c filesPaul Menzel
All the deleted mainboard files contain no code besides some print statements denoting, that the init is executed. If such statements are desired, this should be done in common code so it does not have to be added to each mainboard. Therefore, also delete files with just print statements. Change-Id: I379e4b1e1b1725648c6231bc6954ac3cc655a596 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/12355 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-05mainboard: Remove last_boot NVRAM optionTimothy Pearson
The last_boot NVRAM option was deprecated and removed in commit 3bfd7cc6. Remove the last_boot option from all affected mainboards to eliminate user confusion. Change-Id: I7e201b9cf21dfe5dda156785bad078524098626d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12316 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-14Revert "Remove FSP Rangeley SOC and mohonpeak board support"Martin Roth
This chip is still being used and should not have been deleted. It's a current intel chip, and doesn't even require an ME binary. This reverts commit 959478a763c16688d43752adbae2c76e7764da45. Change-Id: I78594871f87af6e882a245077b59727e15f8021a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11860 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-03Remove FSP Rangeley SOC and mohonpeak board supportAlexandru Gagniuc
mohonpeak is the reference board for Rangeley. I doubt anyone uses it or cares about it. We jokingly refer to it as "Moron Peak". It's code with no known users, so we shouldn't be hauling it around for the eventuality that someone might use it in the future. Change-Id: Id3c9fc39e1b98707d96a95f2a914de6bbb31c615 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11790 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-06-24Kconfig: Get rid of obsolete symbolsMartin Roth
CAR_MIGRATION was removed in commit: cbf5bdfe - CBMEM: Always select CAR_MIGRATION ALT_CBFS_LOAD_PAYLOAD was removed in commit: cf6c9cc2 - Kill ALT_CBFS_LOAD_PAYLOAD MARK_GRAPHICS_MEM_WRCOMB was removed in commit: 30fe6120 - MTRR: Mark all prefetchable resources as WRCOMB. EXTERNAL_MRC_BLOB was removed in commit: 0aede118 - Drop unused EXTERNAL_MRC_BLOB CACHE_ROM is only in Google's codebase. LID_SWITCH is only in Google's codebase. DEFAULT_POST_DEVICE_LPC is only in Sage's codebase. ROMSTAGE_RTC_INIT is only in Sage's codebase, or was never used. HUDSON_NOT_LEGACY_FREE never existed as far as I can tell. MAINBOARD_DO_EDID never existed as far as I can tell. Change-Id: I636ea7584fb47885638dbcd9ccedfafb1ca2c640 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10616 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-23southbridge/intel: Create common IFD Kconfig and MakefileMartin Roth
We've got a lot of duplicated code to set up the IFD/ME/TXE/GBE/ETC. This is the start of creating a common interface for all of them. This also allows us to reduce the chipset dependencies for CBFS_SIZE. Change-Id: Iff08f74305d5ce545b5863915359eeb91eab0208 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10613 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-08Remove empty lines at end of fileElyes HAOUAS
Used command line to remove empty lines at end of file: find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \; Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/10446 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-04-24fsp: Move fsp to fsp1_0Marc Jones
Prepare for FSP 1.1 integration by moving the FSP to a FSP 1.0 specific directory. See follow-on patches for sharing of common code. Change-Id: Ic58cb4074c65b91d119909132a012876d7ee7b74 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/9970 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-23src/mainboard/*/*/board_info.txt: Added Release year for boardsMathias Friman
To simplify browsing the "Supported hardware" list, I added Release year for the hardware from asus, asrock, gigabyte, msi, via, tyan, intel, lenovo, apple, jetway and hp. Still several models and manufacturers to add information to. This is more of a proof-of-concept. The "Release year" will be shown in the wiki page. Change-Id: I6bc14ed06ac7c6b3c9f054b49f08cb9b3dc47947 Signed-off-by: Mathias Friman <mathias@workplays.se> Reviewed-on: http://review.coreboot.org/9963 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-18kconfig: automatically include mainboardsStefan Reinauer
This change switches all mainboard vendors and mainboards to be autoincluded by Kconfig, rather than having to be mentioned explicitly. This means, vendor and mainboard directories are becoming more "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree mainboards / components to be built with a given coreboot version (given that the API did not change) Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: Ib68ce1478a2e12562aeac6297128a21eb174d58a Reviewed-on: http://review.coreboot.org/9295 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-03-05mainboard: Do not redefine DRIVERS_PS2_KEYBOARD Kconfig variableAlexandru Gagniuc
Change-Id: Icc603dfe92360d978221a25ad28517da43942bea Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8498 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-24mainboard: Do not redefine CONSOLE_POST Kconfig variableAlexandru Gagniuc
This option is already defined in console/Kconfig, and is intended to be controlled by the user. Only six boards in the entire tree redefined it, so remove the definition from those boards. Change-Id: I3a65444f63c93c01d78569a9a7eb01158fb290bd Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8457 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-16mainboard/cmos: Delete obsolete commented parametersTimothy Pearson
Change-Id: Iccad79c142a7fcf89dd0fbebe8c07ad9ef019e91 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8459 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
2015-01-06doxygen fixes: fix parameter names to match the functionsMartin Roth
The doxygen parameter names in the comments no longer matched the functions they were attached to. Doxygen complains about extra parameter comments and uncommented parameters in the functions. Change-Id: I21b8a951f8d8d04b07c3779000eeaf1e69fed463 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8101 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-06Remove IRQ_SLOT_COUNT on all boards without PIRQ table.Vladimir Serbinenko
This config is used only to generate PIRQ table. If no such table is supplied there is no need for config. Change-Id: I537d440f53019a6bf7f190446074e75e7420545a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7566 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-01Mark non-executable files non-executablePatrick Georgi
No need to mark Makefiles, C files or devicetrees executable. Change-Id: Ide3a0efc5b14f2cbd7e2a65c541b52491575bb78 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7618 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-28ACPI: Remove CBMEM TOC from GNVSKyösti Mälkki
This existed for ChromeOS but was no longer used with DYNAMIC_CBMEM. See commit a0b4a8d. Change-Id: Iae82498ab729df5682d89e66bb9de96457e91619 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7465 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-08fsp_rangeley: Switch to per-device ACPIVladimir Serbinenko
Change-Id: Ic8b2204a6d08d63ac7f05836bf1424f1ca6ee50e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7046 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-17Add board_info for all Google/Intel boards mitting the fileStefan Reinauer
Change-Id: Iac53462ab3621d96ba15e2fde2800212584246db Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7072 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-09-12payloads/external/SeaBIOS: Allow setting buffers below 0xC0000Martin Roth
Add the option to coreboot to set the SeaBIOS buffers below 0xC0000. This is a requirement on the Intel Rangeley processor because it is designed so that only the processor can write the higher memory areas. This prevents USB and SATA from bus-mastering into the buffers when they're set in the typical 0xE0000 area. This will be set to Y unless defaulted to N by the mainboard or chipset. Push the SeaBIOS buffers down to 0x90000 segment for Mohon Peak Change-Id: I15638605d1c66a2277d4b852796db89978551a34 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6364 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-22Remove dead video.aslVladimir Serbinenko
Change-Id: Iadaa6172347ebb7d367d1faa6ed9462fff07d7e6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6730 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18mainboard/intel/mohonpeak: code cleanupMartin Roth
Code cleanup requested in commit 90957f88 - "mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000" - Change com2 to COM2 in Kconfig text - clean up includes of headers - fix whitespace Change-Id: I828bc4781ee7de95be5546206c5d6033b75293d9 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6607 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18southbridge/intel/fsp_rangeley: fix to include irqroute.h twiceMartin Roth
This matches what was done on baytrail in commit bfca984b - soc/intel/fsp_baytrail: set up for including irqroute.h twice irq_helper.h intentionally gets included into irqroute.asl twice - once for pic mode and once for apic mode. Since people are used to seeing guard statements on the .h files, add the guards to irqroute.h and add a comment to irq_helper.h explaining why they aren't there. Change-Id: I709f9370ce7db1b3ffac2297aeaba5cc670ec20c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6606 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18mainboard/XXX/YYY/dsdt.asl: Whitespace fixMartin Roth
Use tab between "COREBOOT", and comment. This fix was requested in 90957f88 - "mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000" Change-Id: If9fb6158cca95341ab57db1125e85648b616b72c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6601 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-30mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000Martin Roth
Add the Mohon Peak CRB. Updates to come. Change-Id: I0a8496d502bab905c6f35eff9fcd7eda266831ed Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/6371 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 20:21:17 +0000