| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-11-01 | soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi | Subrata Banik |
| 2018-11-30 | cpu/intel/common: Use a common acpi/cpu.asl file | Arthur Heymans |
| 2018-11-23 | mb: Set coreboot as DSDT's manufacturer model ID | Elyes HAOUAS |
| 2018-11-21 | ACPI: Fix DSDT's revision field | Elyes HAOUAS |
| 2015-12-06 | intel/fsp_rangeley: change non-existent config options to #defines | Martin Roth |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-10-14 | Revert "Remove FSP Rangeley SOC and mohonpeak board support" | Martin Roth |
| 2015-10-03 | Remove FSP Rangeley SOC and mohonpeak board support | Alexandru Gagniuc |
| 2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
| 2014-08-18 | mainboard/XXX/YYY/dsdt.asl: Whitespace fix | Martin Roth |
| 2014-07-30 | mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000 | Martin Roth |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |