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path: root/src/mainboard/intel/minnowmax
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2015-03-12intel/fsp_baytrail: Add PCI Root Port IRQ RoutingMartin Roth
This change generates the ASL tables needed for the PCIe bridge routing. It generates this ASL (swizzled for each of the 8 functions) Name(RP1P, Package() { Package() {0x0000ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, Package() {0x0000ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, Package() {0x0000ffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, Package() {0x0000ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, }) Name(RP1A, Package() { Package() {0x0000ffff, 0, 0, 20 }, Package() {0x0000ffff, 1, 0, 21 }, Package() {0x0000ffff, 2, 0, 22 }, Package() {0x0000ffff, 3, 0, 23 }, }) Device(RP01) { Name(_ADR, 0x1c0001) Name(_PRW, Package() { 0, 0 }) Method(_PRT,0) { If(PICM) { Return (RP1A) } Else { Return (RP1P) } } } Change-Id: Id51261c11f8457fe2150f2b646aafc4fe1ffec30 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8429 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-05mainboard: Do not redefine DRIVERS_PS2_KEYBOARD Kconfig variableAlexandru Gagniuc
Change-Id: Icc603dfe92360d978221a25ad28517da43942bea Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8498 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-24mainboard: Do not redefine CONSOLE_POST Kconfig variableAlexandru Gagniuc
This option is already defined in console/Kconfig, and is intended to be controlled by the user. Only six boards in the entire tree redefined it, so remove the definition from those boards. Change-Id: I3a65444f63c93c01d78569a9a7eb01158fb290bd Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8457 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-16mainboard/cmos: Delete obsolete commented parametersTimothy Pearson
Change-Id: Iccad79c142a7fcf89dd0fbebe8c07ad9ef019e91 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8459 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-12-19fsp_baytrail: Remove GPIO_NC1 #defineMartin Roth
The GPIO_NC1 #define was added to handle GPIOs that are not on func0. This is already handled elsewhere in the GPIO code, so is not needed. - Remove the single GPIO_NC1 from platforms using fsp_baytrail - Revert the GPIO_INPUT_PU_10k #define to remove the _func argument. Update everywhere this macro is called. - Remove GPIO_NC1 Change-Id: I32f337af7bc88eab821d9a8c375145b45718275f Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7849 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17intel/minnowmax: Determine board type from GPIOsMartin Roth
SSUS GPIO 5 reflects the Minnowboard Max SKU: --- GPIO 5 low is a 1GB board --- GPIO 5 high is a 2GB (or 4GB in the future) board. This allows us to determine the board type at runtime and configure the FSP appropriately. Change-Id: I9f75df5413d23d63280b601457ea9a1ff020d717 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7797 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-12-06Remove IRQ_SLOT_COUNT on all boards without PIRQ table.Vladimir Serbinenko
This config is used only to generate PIRQ table. If no such table is supplied there is no need for config. Change-Id: I537d440f53019a6bf7f190446074e75e7420545a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7566 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-06fsp_baytrail: Allow selection of USB controller by get_optionMartin Roth
It was requested to be able to update XHCI vs EHCI via get_option, so I've added it here for minnow max. This could get moved to the chipset_fsp_util.c file later, but I'm adding it here for now. More checking needs to be added to this: - Are both controllers enabled in devicetree? If not, we don't want to allow the switch. Change-Id: I4d8d2229cb9fa0cd9068701454b28ffac6d8e767 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7633 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-06intel/minnowmax: Update devicetreeMartin Roth
- Align register values. - Enable both EHCI and XHCI so the choice of port used can be made at runtime. When both are enabled in devicetree, XHCI currently gets disabled by the FSP chipset code. This can be overridden in mainboard code or by a Kconfig entry, but there's a question about whether or not that's desired. - Enable function 1c.0 so the rest of the functions will be seen, even though the function is not actually used. This is a short-term fix, as the correct solution is to determine whether or not any of the other functions are enabled, and not to hide function 0 if they are. I am working on that, but I want to get this in for now. Change-Id: I83ae12c2393024b82a55d0b3a5ffa8782e16107e Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7663 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-05minnowmax board: Update KconfigMartin Roth
- The ROM chip is 8MB, not 4MB. - Default to the 2GB SKU instead of 1GB - that's what's out right now. - Set CBFS size to 3MB - that's what the firmware descriptor is set to. Change-Id: Ic77f5c1e898dca39de573623707ff5f5e5ca9682 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7649 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-05fsp_baytrail: remove register option for TSEG sizeMartin Roth
Set the UPD entry based on the Kconfig value instead of having two separate places that the value needs to be set. Change-Id: I3d32111b59152d0a8fc49e15320c7b5a140228a6 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7490 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2014-12-01Mark non-executable files non-executablePatrick Georgi
No need to mark Makefiles, C files or devicetrees executable. Change-Id: Ide3a0efc5b14f2cbd7e2a65c541b52491575bb78 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7618 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-29mainboard/intel/minnowmax: use Baytrail Gold3 FSPYork Yang
Baytrail Gold3 FSP support memory down configuration. Update Minnow Max to use Gold3 FSP. Set memory down data in devicetree.cb, instead of use different FSP image. Change-Id: Ic03da2d2a1cee5144b9a013d3dd9f982ff043123 Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/7581 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-11-19fsp_baytrail: Update chip.h UPD entries to match names in fspvpd.hMartin Roth
The entries in chip.h are used to set the UPD values. These had originally been shortened and did not match the names of the structure entries in vendorcode/intel/fsp/baytrail/include/fspvpd.h This patch aligns the names. - Update names in chip.h. - Update names in devictree registers for bayley bay and minnow max. - Update names in chipset_fsp_util.c Change-Id: I8d7e34195cec2e63802d7e07e5aed71735556936 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7486 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-29minnowmax: Tell the FSP to set TSEG to 8MBMartin Roth
Minnowboard Max was broken by commit 454625c5 - intel/fsp_baytrail: Fix SMM/SMI because TSEG wasn't set to 8MB by the FSP. The default in the FSP is 1MB. Change-Id: I2e671a6ca0240e931399920c62439c36133789aa Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7240 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-10-17Add board_info for all Google/Intel boards mitting the fileStefan Reinauer
Change-Id: Iac53462ab3621d96ba15e2fde2800212584246db Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7072 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-09-29intel/minnowmax: Enable S3 suspend/resumeMohan D'Costa
This enables S3 Suspend / Resume support for MinnowMax board using Intel's Bay Trail FSP Tested resume from Power Button and Magic Packet. Change-Id: I021122a68c05f2e725cabb8f3946249afe802bbe Signed-off-by: Mohan D'Costa <mohan@ndr.co.jp> Reviewed-on: http://review.coreboot.org/6972 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins)
2014-08-22Remove dead video.aslVladimir Serbinenko
Change-Id: Iadaa6172347ebb7d367d1faa6ed9462fff07d7e6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6730 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-12mainboard/intel/minnowmax: clean up includes & whitespaceMartin Roth
Clean up as requested in commit e6df041b. No functional changes. Change-Id: Iec3f7ee25fd8351c7e13d660e2df6461f7745478 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6597 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-11mainboard/intel/minnowmax: Add MinnowMax mainboardMartin Roth
MinnowMax board using Intel's Bay Trail FSP Working: - Booting from SATA / USB / (USB3 with latest SeaBIOS) Not working: - Boot from SD - S3 Suspend / Resume ***** To configure the FSP ***** Download the Bay Trail FSP and the binary config tool: Modify the standard Bay Trail FSP: run the bct tool with the command line options: bct --bin <Bay Trail FSP Binary> \ --absf src/vendorcode/intel/fsp/baytrail/absf/minnowmax_Xgb.absf \ --bout <path to save the updated FSP to> Here are the required changes for modifying the FSP manually: Enable Memory Down: Enabled DRAM Speed: 1066 MHz DIMM_DWidth: x16 DIMM_Density: 4 Gbit (2GB Minnow Max) / 2 Gbit (1GB Minnow Max) tCL: 7 tRP_tRCD: 7 tWR: 8 tRRD: 6 tRTP: 4 tFAW: 27 Other FSP values can remain the same. ***** To configure the vbios ***** The vbios is in the Bay Trail FSP package. Download Intel's "Binary Modification Program" (BMP) Use it to disable all ports except HDMI on port B. Change-Id: I00d90e0d838d70c9d25c69f5115d0c9d6d19855c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6429 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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