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path: root/src/mainboard/intel/minnow3/bootblock.c
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2020-04-06mainboard/intel: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I1ea2eebfdd43610e42b4cf04409ec76c2e8b0042 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40082 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-18mainboard/[g-p]*: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I426518e8e18de1c8efcfb7ecb0835df3e257dca1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39608 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-15soc/intel/common/block: Add LPC Common code and use it for APLRavi Sarawadi
Add LPC common code to be shared across Intel platforms. Also add LPC library functions to be shared across platforms. Use common LPC code for Apollo Lake soc. Update existing Apollolake mainboard variants {google,intel,siemens} to use new common LPC header file. Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/20659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-22intel/minnow3: Implement and configure GPIO tablesBrenton Dong
Copy GPIO table implementation from the google/reef board except with board variant features removed. Also exlcude CrOS GPIO functions. Remove previous romstage GPIO implementation in brd_gpio.h and romstage.c. Configure GPIO settings for MinnowBoard 3. Change-Id: Id2817dcf2f8f196ecd13c810f7f0010a115db566 Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/18375 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-22mainboard/intel: Add MinnowBoard 3Brenton Dong
This commit adds the initial scaffolding for the MinnowBoard 3 with Apollo Lake silicon. This mainboard is based on Intel's Leafhill CRB with Apollo Lake silicon. In a first step, it concerns only a copy of intel/leafhill directory with name changes. Special adaptations for MinnowBoard 3 mainboard will follow in separate commits. Change-Id: I7563fe37c89511c7035c5bffc9b034b379cfcaf4 Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/18298 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>