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Changes the offsets of some options so that options that span multiple
bytes are byte aligned.
To make the cmos.layout file more consistent some things where moved
around in the cmos.layout of thinkpads X200 and T400.
Change-Id: Ic84a2a5dc6f9c102f041085871c2ed55e2f3692a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Currently, it’s impossible for the user to select `NO_POST`, for boards
selecting it in their config.
```
warning: (BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS &&
BOARD_SPECIFIC_OPTIONS) selects POST_IO which has unmet direct
dependencies (VENDOR_ASUS && (BOARD_ASUS_F2A85_M ||
BOARD_ASUS_F2A85_M_PRO || BOARD_ASUS_F2A85_M_LE) && (BOARD_ASUS_F2A85_M
|| BOARD_ASUS_F2A85_M_PRO) || VENDOR_MSI && BOARD_MSI_MS7721 ||
PC80_SYSTEM && !NO_POST)
```
This is currently done for Intel Mohon Peak, and its descendants.
Selecting the option `POST_IO` in board specific configuration is not a
good idea, as this should be user configurable over Kconfig, and also
the tree-wide defaults should be the same for these options.
Change-Id: Ia4ab0d942b7d66f18466a770ef739109ab0db629
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/18877
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ic22beaa47476d8c600e4081fc5ad7bc171e0f903
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17735
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Make MMCONF_SUPPORT selected with MMCONF_SUPPORT_DEFAULT.
Platforms that remain to have explicit MMCONF_SUPPORT are
ones that should be converted.
Change-Id: Iba8824f46842607fb1508aa7d057f8cbf1cd6397
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17527
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: If3cdfdff60c92e3427f1b285e2bca92e2bb2a1cb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16640
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector
code) the reboot counter stored in `reboot_bits` isn't reset on a reboot
with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR
enabled, later stages (e.g. payload, OS) have to clear the counter too,
when they want to switch to normal boot. So change the bits to (h)ex
instead of (r)eserved.
To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also
remove all occurences of the obsolete `last_boot` bit that have sneaked
in again since 24391321 (mainboard: Remove last_boot NVRAM option).
Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/16157
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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- Change SEABIOS_MALLOC_UPPERMEMORY to using PAYLOAD_CONFIGFILE.
- Add saved seabios .config with CONFIG_MALLOC_UPPERMEMORY unset.
- Remove fixed microcode location.
Change-Id: I8b723edf6d6b5542f118e9e0e1aee8104d9cde86
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12635
Tested-by: build bot (Jenkins)
Reviewed-by: David Guckian <david.guckian@intel.com>
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Kconfig symbols CONFIG_ACPI_INCLUDE_PMIO and CONFIG_ACPI_INCLUDE_GPIO
were never added to the coreboot codebase when the Rangeley code was
brought in from Sage. These symbols disabled ACPI code that was unused
because it caused dmesg warnings due to conflicts with drivers trying to
claim the same addresses as the ACPI code. Because it could be used on
some other platforms, it was left in instead of being completely
removed.
- Change the Kconfig symbol names to simple #defines in the mainboard
code.
- Add the #defines along with comments to the reference platform.
- Hook everything together in dsdt.asl
- Update new mainboard littleplains the same way.
Change-Id: I1f62157c6e447ea9b7207699572930e4711fc3e0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12552
Reviewed-by: David Guckian <david.guckian@intel.com>
Tested-by: build bot (Jenkins)
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Devices that have their interrupt routing set to A, A, A, A don't get
any interrupt values assigned because that series evaluates to 0. The
code that sets the interrupt values checks to make sure a value is set
by verifying that it's not 0. On Bay Trail, these are all
single-function graphics devices, so by changing one of the unused
interrupt lines from A to any other value, it assigns the values
correctly.
This issue did not affect ACPI interrupt routing.
This is just a workaround, and the root issue still needs to be fixed.
Change-Id: I4e6fe56084cbe86b309da15d61b296f1936458ec
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12630
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This adds a new mainboard: Little Plains for Intel's atom c2000
It was based on Mohon Peak board with some minor changes
This board is not available as standalone product
It is a managment board for
Intel Ethernet Multi-host Controller FM10000 Series
The FSP package is available from Intel: https://www.intel.com/fsp
Change-Id: I28127a858106ed35d26e235f0c6393c20ed14350
Signed-off-by: Marcin Wojciechowski <marcin.wojciechowski@intel.com>
Reviewed-on: https://review.coreboot.org/12503
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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