coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2016-11-22	Remove explicit select MMCONF_SUPPORT	Kyösti Mälkki
	Make MMCONF_SUPPORT selected with MMCONF_SUPPORT_DEFAULT. Platforms that remain to have explicit MMCONF_SUPPORT are ones that should be converted. Change-Id: Iba8824f46842607fb1508aa7d057f8cbf1cd6397 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17527 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-20	src/mainboard/getac - kontron: Add space around operators	Elyes HAOUAS
	Change-Id: If3cdfdff60c92e3427f1b285e2bca92e2bb2a1cb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16640 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-17	mainboard: Clean up boot_option/reboot_bits in cmos.layout	Nico Huber
	Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector code) the reboot counter stored in `reboot_bits` isn't reset on a reboot with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR enabled, later stages (e.g. payload, OS) have to clear the counter too, when they want to switch to normal boot. So change the bits to (h)ex instead of (r)eserved. To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also remove all occurences of the obsolete `last_boot` bit that have sneaked in again since 24391321 (mainboard: Remove last_boot NVRAM option). Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/16157 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-12-08	intel/littleplains: Update with recent changes to mohonpeak	Martin Roth
	- Change SEABIOS_MALLOC_UPPERMEMORY to using PAYLOAD_CONFIGFILE. - Add saved seabios .config with CONFIG_MALLOC_UPPERMEMORY unset. - Remove fixed microcode location. Change-Id: I8b723edf6d6b5542f118e9e0e1aee8104d9cde86 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12635 Tested-by: build bot (Jenkins) Reviewed-by: David Guckian <david.guckian@intel.com>
2015-12-06	intel/fsp_rangeley: change non-existent config options to #defines	Martin Roth
	Kconfig symbols CONFIG_ACPI_INCLUDE_PMIO and CONFIG_ACPI_INCLUDE_GPIO were never added to the coreboot codebase when the Rangeley code was brought in from Sage. These symbols disabled ACPI code that was unused because it caused dmesg warnings due to conflicts with drivers trying to claim the same addresses as the ACPI code. Because it could be used on some other platforms, it was left in instead of being completely removed. - Change the Kconfig symbol names to simple #defines in the mainboard code. - Add the #defines along with comments to the reference platform. - Hook everything together in dsdt.asl - Update new mainboard littleplains the same way. Change-Id: I1f62157c6e447ea9b7207699572930e4711fc3e0 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12552 Reviewed-by: David Guckian <david.guckian@intel.com> Tested-by: build bot (Jenkins)
2015-12-06	Rangeley: Change A, A, A, A INT routing to A, A, A, B	Martin Roth
	Devices that have their interrupt routing set to A, A, A, A don't get any interrupt values assigned because that series evaluates to 0. The code that sets the interrupt values checks to make sure a value is set by verifying that it's not 0. On Bay Trail, these are all single-function graphics devices, so by changing one of the unused interrupt lines from A to any other value, it assigns the values correctly. This issue did not affect ACPI interrupt routing. This is just a workaround, and the root issue still needs to be fixed. Change-Id: I4e6fe56084cbe86b309da15d61b296f1936458ec Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12630 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-30	mainboard/intel: Add Little Plains	Marcin Wojciechowski
	This adds a new mainboard: Little Plains for Intel's atom c2000 It was based on Mohon Peak board with some minor changes This board is not available as standalone product It is a managment board for Intel Ethernet Multi-host Controller FM10000 Series The FSP package is available from Intel: https://www.intel.com/fsp Change-Id: I28127a858106ed35d26e235f0c6393c20ed14350 Signed-off-by: Marcin Wojciechowski <marcin.wojciechowski@intel.com> Reviewed-on: https://review.coreboot.org/12503 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>