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path: root/src/mainboard/intel/kunimitsu/devicetree.cb
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2015-10-27intel/kunimitsu: USB Phy settings and Skip UART2 init in FSPRizwan Qureshi
FSP 1.7.0 provides UPD to configure USB phy settings update the same for kunimitsu. FSP 1.7.0 also provides UPD to indicate FSP not to reinitialise UART2 controller during MemoryInit. BRANCH=none BUG=chrome-os-partner:45684,chrome-os-partner:41374,chrome-os-partner:42284 TEST=build for Kunimitsu, boot on FAB3, Also checked for Boot from USB, Boot from eMMC, USB Audio, Onboard Audio, Touch, Wifi, S3 entry/resume CQ-DEPEND=CL:303661 Change-Id: Ie0a545c954f472cc822b63786d40399ec93d5166 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 90296e04942c70d972c225fc75dfab6de44d10ed Original-Change-Id: If79e81ef3323e782e96db307d89a01c14174b435 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/304032 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12145 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17kunimitsu: Enable wake-on-wifiDuncan Laurie
- Assign GPE DW0 to GPP_B block - Enable GPP_B16 as ACPI_SCI for wake - Define PCIe WLAN device in ACPI with GPE0_DW0_16 for _PRW Note that current designs cannot wake from Deep S3 via wifi. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I1fe15a5a9b3d868a0e4f1bfb102b69f024c3aa48 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: de9dfee840246866a8dcca2e1c42c0292e820529 Original-Change-Id: I926d74b6bcf6d64c3db61ed23d7c17b51a98b052 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298232 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11651 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-16kunimitsu: Disable Deep S3 on kunimitsu platformSubrata Banik
This patch will reset Deep S3 flag, hence S3 will work. BUG=chrome-os-partner:40635 BRANCH=None TEST=Build and Boot Kunimitsu and verify S3 is working. Change-Id: Iad87b7a8f7bf560861a270a8c19153cfc3850bc4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fbfaa29041be49e4c39d19cb94f01ad10d12c7d5 Original-Change-Id: I5ae1738c5de1bee1ad9a45ebde074a6a378492af Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/297903 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11643 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-10kunimitsu: Clean up mainboard code to match gladosDuncan Laurie
Clean up the intel/kunimitsu mainboard code to match the code and cleanups in glados. Many of these are trivial changes that do not impact things in a meaningful way but will make it easier to diff the code and keep the mainboards in sync. - use relative path for mainboard includes to make porting easier - fix trivial style issues to match glados so diffs are clean - pull GPIO configuration into gpio.h and use from there - remove thermal.h as it is not used on this board - make info message BIOS_INFO instead of BIOS_ERR - add support for SPD manufacturer and part number in SMBIOS BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I64a053bcec0e0ff25a57f65659f391ab64d9a11a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e47f0fd3e00a665f07098c7ea0018d51b105d1be Original-Change-Id: Ib787f3ccc63115de48c4d608ca2bd81b58d24b6c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297752 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11576 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08kunimitsu: Clean up devicetree.cbDuncan Laurie
Fix the PCI device list comments to be consistent between mainboards and remove unused and incorrect register settings. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: Ib1c0eb80c57661502a4d4cfb4622a34effaa1c4a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 17c4f0d306194e7086f39f7ab560841999c318d8 Original-Change-Id: Ia1c138e52cbc3e81c0d12aa97d7f564e723d61f9 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297339 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11562 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08kunimitsu: Fix incorrect comment format in devicetree.cbDuncan Laurie
The devicetree.cb compiler can't handle C style /**/ comments, they need to be shell-style #. Due to a last minute formatting change in my commit to enable USB ports this broke the kunimitsu build. BUG=chrome-os-partner:44662 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I7a77f0f51345f779fcae43338cdc078bc91bb51c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6454b377f865ec3d4e426fce3259f4df5d513ef5 Original-Change-Id: I19bde397018890db37257b55d0481e0c9f3a41f2 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296302 Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11554 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08kunimitsu: Disable unused USB portsDuncan Laurie
Enable only the USB ports that are connected on-board or to an external port, all others will be disabled. BUG=chrome-os-partner:44662 BRANCH=none TEST=emerge-kunimitsu coreboot, change verified in schematic but not tested Change-Id: I909a6fab553bba829349dd08fa9cc3f26e5adeb2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1b0ce28d093e3b12273d7e0f56b47fb5b13d712f Original-Change-Id: I0c4b7de6e559595efa97d756e43f8398feccdffd Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296036 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11549 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-27kunimitsu: Enable SMBus device in devicetreeNaveen Krishna Chatradhi
this patch enables SMBus in device tree for kunimitsu board. BRANCH=none BUG=none TEST=built for kunimitsu; booted on kunimitsu fab3 and verified with lspci Original-Change-Id: I3b2b8c202b71c2a0c602169841978ed0c4d8bf8d Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292971 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Id20e6cafda8664bd0ae3a5acecdd66c58c220694 Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Reviewed-on: http://review.coreboot.org/11276 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-27Kunimitsu: enable deep S5Naveen Krishna Chatradhi
This patche enables the deep S5 and disables Deep S3. Kunimitsu does not resume from deep S3. This change will unblock the S3 resume path on kunimitsu board. BRANCH=None BUG=chrome-os-partner:42331 TEST=Built and booted on kunimitsu; check s3 works. Original-Change-Id: Ia828a39bceef615fd194bb3614ba2de87c3af805 Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291250 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I07b95a324a27ab658e80674686b47b86412ea097 Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Reviewed-on: http://review.coreboot.org/11274 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-19Kunimitsu: Fix Wifi, kepler RP mapping and enable ClkReqSupportPratik Prajapati
(1) Wifi is connected on RP1 which is 1c.0 , so enabling 1c.0 and disabling 1d.0 (2) kepler is on RP5 which is 1c.4, so enabling it (3) enabling ClkReqSupport for RP1 and RP5 so that L1 substates can get enabled. BRANCH=None BUG=chrome-os-partner:43738 TEST=Built and boot for Kunimitsu. checked all PCIe powersaving states (LTR, L1, L1S) are enabled Original-Change-Id: I525661399d1a4d939b53d5ed5f7991598b84ddcd Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293482 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ib9a771a6ec137217668fb0385efc13b1824772b4 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: http://review.coreboot.org/11237 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-19Kunimitsu: Enable root ports and clkreqsPravin Angolkar
This patch enables the root ports and configures the clock req numbers as per the design On kunimitsu FAB3 board with D0 MCP Root port 1 --> Wifi card --> clkreq 1 Root port 4 --> Kepler VP8/VP9--> clkreq 2 BRANCH=None BUG=chrome-os-partner:43324 CQ-DEPEND=CL:*224327, CL:*224328 TEST=Built for Kunimitsu and Boot Kunimitsu board with D0 MCP Original-Change-Id: I4e110d2d07efbfa7a306852301cd1cd89027b2ba Original-Signed-off-by: Pravin Angolkar <pravin.k.angolkar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/290051 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Change-Id: I6d66c78496ac3f43e07d96feefed35cf50da6aa1 Signed-off-by: Pravin Angolkar <pravin.k.angolkar@intel.com> Reviewed-on: http://review.coreboot.org/11232 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-14skylake: remove ec_smi_gpio and alt_gp_smi_enAaron Durbin
The ec_smi_gpio and alt_gp_smi_en devicetree options are goign to be removed. The plan for skylake is to set the settings by the mainboard through either gpio pad configuration or through helper functions. Moreover, these values only allow *1* SMI GPIO configuration in that the following has to be true: alt_gp_smi_en = 1 << (ec_smi_gpio % 24) If not, then another gpio(s) from the same group has the SMI_EN bit set for it. Lastly, remove all the subsequent dependencies as they are no longer used: enable_alt_smi() and gpio_enable_group(). BUG=chrome-os-partner:43778 BRANCH=None TEST=None Original-Change-Id: I749a499c810d83de522a2ccce1dd9efb0ad2e20a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291931 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I2e1cd6879b76923157268a1449c617ef2aada9c4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11204 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14kunimitsu sklrvp: remove unused IedSizeAaron Durbin
The skylake code is using IED_REGION_SIZE instead of devicetree.cb. Drop the the option from the device trees. BUG=chrome-os-partner:43636 BRANCH=None TEST=None Original-Change-Id: Ib252266060fbc6ed0eeaac19a6b79c173c6c9a13 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290932 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Trybot-Ready: David James <davidjames@chromium.org> Change-Id: Ib08628e163ac27d4c49eddcbec6cab3252abd4aa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11200 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-21kunimitsu: Update Serial IO modes in devicetreeNaveen Krishna Chatradhi
This patch updates the Serial IO modes for UART 1 and 2 in devicetree for kunimitsu boards. UART1 are disabled and UART2 is in PCI mode. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for kunimitsu and tested LPSS logs on Kunimitsu. Change-Id: I5a46ab9e0b792478ee2e0845aeab1443423a2fac Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 38c7b963a9d679ee5106c5343e1173d0b5056627 Original-Change-Id: I39cbb6bb0991e5f9b3365adaf6b24818d112cd1a Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284825 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/11001 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-17mainboard/intel: Add Skylake based Kunimitsu boardLee Leahy
Initial files to support the Kunimitsu board. Matches chromium tree at 927026db This board uses the Skylake FSP 1.1 image and does not build without the FspUpdVpd.h file. BRANCH=none BUG=None TEST=Build and run ChromeOS on kunimitsu Change-Id: I1017a66bc811af51a0921e864b589ce2cb618082 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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