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path: root/src/mainboard/intel/kblrvp
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2017-03-27ec: Use EC_ENABLE_LID_SWITCH for all mainboards with LID using chromeecFurquan Shaikh
Instead of defining a separate LID device for mainboards using chromeec, define EC_ENABLE_LID_SWITCH for these boards. Change-Id: Iac58847c2055fa27c19d02b2dbda6813d6dec3ec Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18964 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-15intel/skylake: Fix bug in VR configuration with FSP 2.0Duncan Laurie
With the move to FSP 2.0 the number of VR types supported was reduced to 4, and the VR_RING type is no longer present. This means all existing boards using FSP 2.0 are incorrectly passing VR configuration into FSP as the values corresponding to "GT Sliced" and "GT Unsliced" have changed. Fix this by updating the skylake SOC VR handling to account for changes in the FSP configuration and no longer provide VR_RING type when using FSP 2.0. BUG=b:36228330 BRANCH=none TEST=manual: build and boot on Eve Change-Id: I59eea9fba006a4c235d7b42d07fdc6e4f44f7351 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18818 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-12-16mb/intel/kblrvp: Increase preram cbmem console sizeNaresh G Solanki
Some part of preram cbmem console output is truncated. Increase preram cbmem console size to 0xd00 to avoid the same. Change-Id: Idbcbb3d1f433668a0e5375679f56fbe562d39ddd Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17840 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-03mainboard/intel/kblrvp: Enabling Kaby Lake RVP7Barnali Sarkar
Add support for Kaby Lake RVP7 board * Add RVP7 board support in Kconfig * Override default descriptor and ME binary paths in Kconfig since those binaries will differ for RVP3 and RVP7 * Add RVP7 board name in board_info.txt and Kconfig.name * Add devicetree.cb for RVP7 in the variants path * Add gpio.h for RVP7 in variants/include/variant path * Made board specific code for retrieving spd, i.e., in RVP7 there is non-soldered DIMMs, so SPD is read through smbus, unlike RVP3 where memory DIMMs are soldered down with board. Hence for RVP3, the spd binaries will be fixed and can be kept as binary file in cbfs. BUG=none BRANCH=none TEST=Built and boot Kaby Lake RVP7 Change-Id: I6f3d17d857bad1b5cf39f0bc900c760fee72da48 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/17637 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30mb/intel/kblrvp: Add Variant board support for KBLRVPBarnali Sarkar
Add support of Variant board model for existing intel/kblrvp, since there might be more RVP board supports under intel/kblrvp. Existing is for KBL RVP3 board. BUG=none BRANCH=none TEST=Built and boot Kaby Lake RVP3 Change-Id: I041a07a273dbb77e422d48591f06b5f1011cd9f7 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/17630 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-30mb/intel/kblrvp: Use common lib spd_bin to get spdNaresh G Solanki
Use common lib spd_bin to get spd. Change-Id: If94413fc36a98f7694f560955bbb80abefe32166 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17435 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30mainboard/intel/kblrvp: Revert back USB OC pin programmingBarnali Sarkar
With commit 2c3054c1(soc/intel/skylake: Add USB Port Over Current (OC) Pin programming) USB OC pin programming is already initiated from devicetree.cb, hence remove it from ramstage.c. BUG=none BRANCH=none TEST=Built and booted KBLRVP from USB device Change-Id: Icb47533aa57f208d5a52560db924169b908c7a88 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/17635 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-28soc/intel/skylake: Add USB Port Over Current (OC) Pin programmingSubrata Banik
Program USB Overcurrent pins as per board schematics definition. BUG=none BRANCH=none TEST=Build and boot kunimitsu from USB device. Change-Id: I6aeb65953c753e09ad639469de7d866a54f42f11 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17570 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-11-22Remove explicit select MMCONF_SUPPORTKyösti Mälkki
Make MMCONF_SUPPORT selected with MMCONF_SUPPORT_DEFAULT. Platforms that remain to have explicit MMCONF_SUPPORT are ones that should be converted. Change-Id: Iba8824f46842607fb1508aa7d057f8cbf1cd6397 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17527 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-17mb/intel/kblrvp: Remove unused configs in KconfigNaresh G Solanki
Remove unused drivers & nhlt in Kconfig. Change-Id: Ic1e8a98a77a0061e749019665f955b921f85975e Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17427 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-14intel/kblrvp: Enable TPMNaresh G Solanki
Add choice to build without TPM, TPM 1.2 support or TPM 2.0 support. Additionally configure lpc clock pad used with LPC TPM & update devicetree.cb. Change-Id: I1c24fdefa6e73637b3037ecf118559abe5fde300 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17367 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-11kblrvp: Add support for Hynix memoryNaresh G Solanki
Add support for hynix memory variant of RVP3. Change-Id: Ic1f8630b36eb131b70c5e3b620957d9602da11ee Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17339 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-11mainboard/intel/kblrvp: Add support to read board ID from ECAamir Bohra
Add a function to identify an Intel RVP board by querying EC Change-Id: I21337000827639fb8f22c5ee9bc5d86f1ebe1e74 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/17283 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10intel/kblrvp: Program I/O expanderNaresh G Solanki
Program I/O expander connected on I2C bus 4 Change-Id: I1a431f50e7b06446399a7d7cb9490615818147e7 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17338 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-08intel/kblrvp: Update mainboard configurationNaresh G Solanki
Update devicetree.cb as per RVP3 mainboard. * Enable & configure PCIE ports, * Enable & configure USB ports, * Enable SSIC for WWAN, * Disable unused I2C ports, * Disable deep S5, * Disable HDA, * Update VR config, Updated gpio.h to disable pull down for SoC power button. Change-Id: I235a1d44dabef16ded2aaad13aef36ca57f37c8e Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17247 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-07mainboard/intel/kblrvp: Remove unused code in dptf.aslNaresh G Solanki
Remove unused code from dptf.asl Change-Id: Icaa675fd1052367457d6e50d51d567e7db02fd42 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17249 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-07mainboard/intel/kblrvp: Configure usb over current pin & cdclockNaresh G Solanki
Configure overcurrent pins for various usb ports. Configure CdClock to 3. Change-Id: I57f1feb7e03c5bc7b125ea7e0735481fee91b6f6 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17251 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-07mainboard/intel/kblrvp: Enable Build with ChromeOSNaresh G Solanki
Enable building with ChromeOS support. Change-Id: I9fbb7422be205b304253478a70e334a63afab71f Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17250 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-07mainboard/intel/kblrvp: Add Chrome EC switchNaresh G Solanki
Add Chrome EC switch to enable building with/without Chrome EC. Change-Id: Iaa8102cba0a454a24149d29f044a2284cd29e28b Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17248 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-03mainboard/intel/kblrvp: Update onboard memory specific configsNaresh G Solanki
1. Update dq, dqs map & Rcomp strength & Rcomp target. 2. Fix rvp3.spd.hex byte 2 to 0x0F(JEDEC LPDDR3 memory type). Change-Id: I7efc3499b915d1e414cfe914830232993ef10ba2 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17162 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2016-11-03mainboard/intel/kblrvp: Update gpio.h, spd.h & mainboard.cNaresh G Solanki
1. Update gpio.h to set proper pad config for Kaby Lake RVP3. 2. Set spd index to zero. 3. Remove nhlt specific init. Change-Id: I41a312d92acd2c111465a5e8f1771158e3f33e2b Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17161 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-27skylake: Use COMMON_FADTDuncan Laurie
Remove the FADT from the individual mainboards and select and use COMMON_FADT in the SOC instead. Set the ACPI revision to 5. Change-Id: Ieb87c467c71bc125f80c7d941486c2fbc9cd4020 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17138 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-25mainboard/intel/kblrvp: Initial commit for Intel Kaby Lake RVP3Naresh G Solanki
Add support for Kaby Lake RVP3. Use kunimitsu at commit 028200f as base. Kabylake RVP3 is based on Kabylake-Y with onboard Dual Channel LPDDR3 DIMM. * Update board name to kblrvp * Remove fsp 1.1 specific code( As Kabylake uses fsp2.0) * Remove board id function. * Remove unused spd & add rvp3 spd file. This is an initial commit does not have full support to boot. Will add more CLs to boot Chrome OS with depthcharge. Change-Id: Id8e32c5b93fc32ba84278c5c5da8f8e30c201bea Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17032 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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