coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2016-11-30	mb/intel/kblrvp: Add Variant board support for KBLRVP	Barnali Sarkar
	Add support of Variant board model for existing intel/kblrvp, since there might be more RVP board supports under intel/kblrvp. Existing is for KBL RVP3 board. BUG=none BRANCH=none TEST=Built and boot Kaby Lake RVP3 Change-Id: I041a07a273dbb77e422d48591f06b5f1011cd9f7 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/17630 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-30	mb/intel/kblrvp: Use common lib spd_bin to get spd	Naresh G Solanki
	Use common lib spd_bin to get spd. Change-Id: If94413fc36a98f7694f560955bbb80abefe32166 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17435 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-11	kblrvp: Add support for Hynix memory	Naresh G Solanki
	Add support for hynix memory variant of RVP3. Change-Id: Ic1f8630b36eb131b70c5e3b620957d9602da11ee Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17339 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-03	mainboard/intel/kblrvp: Update onboard memory specific configs	Naresh G Solanki
	1. Update dq, dqs map & Rcomp strength & Rcomp target. 2. Fix rvp3.spd.hex byte 2 to 0x0F(JEDEC LPDDR3 memory type). Change-Id: I7efc3499b915d1e414cfe914830232993ef10ba2 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17162 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2016-11-03	mainboard/intel/kblrvp: Update gpio.h, spd.h & mainboard.c	Naresh G Solanki
	1. Update gpio.h to set proper pad config for Kaby Lake RVP3. 2. Set spd index to zero. 3. Remove nhlt specific init. Change-Id: I41a312d92acd2c111465a5e8f1771158e3f33e2b Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17161 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-25	mainboard/intel/kblrvp: Initial commit for Intel Kaby Lake RVP3	Naresh G Solanki
	Add support for Kaby Lake RVP3. Use kunimitsu at commit 028200f as base. Kabylake RVP3 is based on Kabylake-Y with onboard Dual Channel LPDDR3 DIMM. * Update board name to kblrvp * Remove fsp 1.1 specific code( As Kabylake uses fsp2.0) * Remove board id function. * Remove unused spd & add rvp3 spd file. This is an initial commit does not have full support to boot. Will add more CLs to boot Chrome OS with depthcharge. Change-Id: Id8e32c5b93fc32ba84278c5c5da8f8e30c201bea Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17032 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>