coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
	This patch is a raw application of find src/ -type f \| xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-16	mb/intel/kblrvp: Add new Kaby lake RVP11 support	Praveen hodagatta pranesh
	The RVP11 is a dual-channel DDR4 SO-DIMM on skylake H platform. This patch add following chages - Add overridetree.cb for RVP11 - Select skylake PCH-H chipset config for RVP11. - Add GPIO table as per board schematics. - Add audio verb table for RVP11. - Set the UserBd UPD to BOARD_TYPE_DESKTOP. BUG=None TEST= Build and flash, confirm boot into yocto OS on KBL RVP11 platform. verified PCI, USB, ethernet, SATA, display, audio and power functionalities. Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Change-Id: Id86f56df06795601cc9d7830766e54396d218e00 Reviewed-on: https://review.coreboot.org/c/29809 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-18	include/device: Split i2c.h into three	Nico Huber
	Split `i2c.h` into three pieces to ease reuse of the generic defi- nitions. No code is changed. * `i2c.h` - keeps the generic definitions * `i2c_simple.h` - holds the current, limited to one controller driver per board, devicetree independent I2C interface * `i2c_bus.h` - will become the devicetree compatible interface for native I2C (e.g. non-SMBus) controllers Change-Id: I382d45c70f9314588663e1284f264f877469c74d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-01	intel/kblrvp: Enable audio in RVP7 and RVP3	Naresh G Solanki
	Enable audio: * Add verb table for ALC286 & ALC298 * Enable virtual channel 1 for DmiVc1 & HdaVc1. TEST= Build for kblrvp3 as well as kblrvp7. Boot to OS & verified working of audio on both the boards. Change-Id: Id27e3cf585b93ed4131d7bf3d3b53d3f5404b18e Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/18875 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-30	mb/intel/kblrvp: Add Variant board support for KBLRVP	Barnali Sarkar
	Add support of Variant board model for existing intel/kblrvp, since there might be more RVP board supports under intel/kblrvp. Existing is for KBL RVP3 board. BUG=none BRANCH=none TEST=Built and boot Kaby Lake RVP3 Change-Id: I041a07a273dbb77e422d48591f06b5f1011cd9f7 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/17630 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-30	mainboard/intel/kblrvp: Revert back USB OC pin programming	Barnali Sarkar
	With commit 2c3054c1(soc/intel/skylake: Add USB Port Over Current (OC) Pin programming) USB OC pin programming is already initiated from devicetree.cb, hence remove it from ramstage.c. BUG=none BRANCH=none TEST=Built and booted KBLRVP from USB device Change-Id: Icb47533aa57f208d5a52560db924169b908c7a88 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/17635 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10	intel/kblrvp: Program I/O expander	Naresh G Solanki
	Program I/O expander connected on I2C bus 4 Change-Id: I1a431f50e7b06446399a7d7cb9490615818147e7 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17338 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-07	mainboard/intel/kblrvp: Configure usb over current pin & cdclock	Naresh G Solanki
	Configure overcurrent pins for various usb ports. Configure CdClock to 3. Change-Id: I57f1feb7e03c5bc7b125ea7e0735481fee91b6f6 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17251 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-25	mainboard/intel/kblrvp: Initial commit for Intel Kaby Lake RVP3	Naresh G Solanki
	Add support for Kaby Lake RVP3. Use kunimitsu at commit 028200f as base. Kabylake RVP3 is based on Kabylake-Y with onboard Dual Channel LPDDR3 DIMM. * Update board name to kblrvp * Remove fsp 1.1 specific code( As Kabylake uses fsp2.0) * Remove board id function. * Remove unused spd & add rvp3 spd file. This is an initial commit does not have full support to boot. Will add more CLs to boot Chrome OS with depthcharge. Change-Id: Id8e32c5b93fc32ba84278c5c5da8f8e30c201bea Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17032 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>