coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2016-11-08	intel/kblrvp: Update mainboard configuration	Naresh G Solanki
	Update devicetree.cb as per RVP3 mainboard. * Enable & configure PCIE ports, * Enable & configure USB ports, * Enable SSIC for WWAN, * Disable unused I2C ports, * Disable deep S5, * Disable HDA, * Update VR config, Updated gpio.h to disable pull down for SoC power button. Change-Id: I235a1d44dabef16ded2aaad13aef36ca57f37c8e Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17247 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-03	mainboard/intel/kblrvp: Update gpio.h, spd.h & mainboard.c	Naresh G Solanki
	1. Update gpio.h to set proper pad config for Kaby Lake RVP3. 2. Set spd index to zero. 3. Remove nhlt specific init. Change-Id: I41a312d92acd2c111465a5e8f1771158e3f33e2b Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17161 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-25	mainboard/intel/kblrvp: Initial commit for Intel Kaby Lake RVP3	Naresh G Solanki
	Add support for Kaby Lake RVP3. Use kunimitsu at commit 028200f as base. Kabylake RVP3 is based on Kabylake-Y with onboard Dual Channel LPDDR3 DIMM. * Update board name to kblrvp * Remove fsp 1.1 specific code( As Kabylake uses fsp2.0) * Remove board id function. * Remove unused spd & add rvp3 spd file. This is an initial commit does not have full support to boot. Will add more CLs to boot Chrome OS with depthcharge. Change-Id: Id8e32c5b93fc32ba84278c5c5da8f8e30c201bea Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17032 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>