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2022-12-27mainboard/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I4f2f02623b060ef0ebefc5aceb713c77a8b1e9a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71523 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2021-10-05src/mainboard to src/security: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-13mb/intel/latest mainboards: Get rid of power button device in corebootSubrata Banik
Refer to commit d7b88dc (mb/google/x86-boards: Get rid of power button device in coreboot) This change gets rid of the generic hardware power button from all intel mainboards and relies completely on the fixed hardware power button. Change-Id: I8f9d73048041d42d809750fdb52092f40ab8f11f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-12mb/intel: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated buils/dsdt.dsl for intel/kblrvp11 are same. Change-Id: I41195be171b48f41fe2955e4639d8b770853d483 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-21mb/intel: Drop unneeded empty linesElyes HAOUAS
Change-Id: I3fdc521d30155c4275c336afe03244311f584e71 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44617 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06mainboard/intel: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I1ea2eebfdd43610e42b4cf04409ec76c2e8b0042 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40082 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-18mainboard/[g-p]*: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I426518e8e18de1c8efcfb7ecb0835df3e257dca1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39608 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-27mb/google/kblrvp: Add camera devices power sequencing through ACPI power ↵V Sowmya
resources This patch controls the camera devices power through ACPI power resource. * Add Opregions for PMIC1 and PMIC2, * TI_PMIC_POWER_OPREGION * TI_PMIC_VR_VAL_OPREGION * TI_PMIC_CLK_OPREGION * TI_PMIC_CLK_FREQ_OPREGION * Add power resources for sensors and VCM, * OVTH for CAM0 * OVFI for CAM1 * VCMP for VCM * Implement _ON and _OFF methods for sensor and VCM module's power on and power off sequences. BUG=none BRANCH=none TEST=Build and boot kblrvp. Dump and verify that the generated DSDT table has the required entries. Verified that sensor probe is successful. Change-Id: I02c4784ab3f4d6e1f0e657ad50b727ff11da8b9c Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-27mb/google/kblrvp: Configure ports and endpoints for sensor and CIO2 devicesV Sowmya
Bind the camera sensor and CIO2 devices through the ports and endpoints configuration available in _DSD ACPI object. * Port represents an interface in a device. * Endpoint represents a connection to that interface. BUG=none BRANCH=none TEST=Build and boot kblrvp. Dump and verify that the generated DSDT table has the required entries. Change-Id: If328864dbb61586a4887c7fcae740a12eda7cc92 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-27mainboard/intel/kblrvp: Add MIPI camera supportV Sowmya
This patch adds mipi_camera.asl and enables I2C2, I2C3, CIO2 and IMGU devices, * Add TPS68470 PMIC1 and PMIC2 related ACPI objects. * Add OV cameras related ACPI objects. * Add Dongwoon AF DAC related ACPI objects. * SSDB: Sensor specific database for camera sensor. * CAMD: ACPI object to specify the camera device type. KBLRVP has two PMIC's sitting on I2C2 and I2C3. CAM0 and CAM1 power requirements are handled by PMIC1 and PMIC2 respectively. BUG=none BRANCH=none TEST=Build and boot kblrvp. Dump and verify that the generated DSDT table has the required entries. Change-Id: Ibaf26dad74ca1e7c9f415ae75c4ed8558ad99e2f Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-24*.asl: Remove obsolete reference to TPM ASL filePatrick Rudolph
TPM ACPI entries are automatically generated, and the old static TPM ASL file is obsolete. Remove the reference to this obsolete static and empty ASL file. Delete src/drivers/pc80/tpm/acpi/tpm.asl. Change-Id: I6163e6d59c53117ecbbbb0a6838101abb468de36 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19291 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-27ec: Use EC_ENABLE_LID_SWITCH for all mainboards with LID using chromeecFurquan Shaikh
Instead of defining a separate LID device for mainboards using chromeec, define EC_ENABLE_LID_SWITCH for these boards. Change-Id: Iac58847c2055fa27c19d02b2dbda6813d6dec3ec Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18964 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30mb/intel/kblrvp: Add Variant board support for KBLRVPBarnali Sarkar
Add support of Variant board model for existing intel/kblrvp, since there might be more RVP board supports under intel/kblrvp. Existing is for KBL RVP3 board. BUG=none BRANCH=none TEST=Built and boot Kaby Lake RVP3 Change-Id: I041a07a273dbb77e422d48591f06b5f1011cd9f7 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/17630 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-07mainboard/intel/kblrvp: Remove unused code in dptf.aslNaresh G Solanki
Remove unused code from dptf.asl Change-Id: Icaa675fd1052367457d6e50d51d567e7db02fd42 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17249 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-07mainboard/intel/kblrvp: Add Chrome EC switchNaresh G Solanki
Add Chrome EC switch to enable building with/without Chrome EC. Change-Id: Iaa8102cba0a454a24149d29f044a2284cd29e28b Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17248 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-25mainboard/intel/kblrvp: Initial commit for Intel Kaby Lake RVP3Naresh G Solanki
Add support for Kaby Lake RVP3. Use kunimitsu at commit 028200f as base. Kabylake RVP3 is based on Kabylake-Y with onboard Dual Channel LPDDR3 DIMM. * Update board name to kblrvp * Remove fsp 1.1 specific code( As Kabylake uses fsp2.0) * Remove board id function. * Remove unused spd & add rvp3 spd file. This is an initial commit does not have full support to boot. Will add more CLs to boot Chrome OS with depthcharge. Change-Id: Id8e32c5b93fc32ba84278c5c5da8f8e30c201bea Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17032 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-21 06:16:17 +0000