coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2020-04-01	soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC	Aamir Bohra
	Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop referring from soc/intel/tigerlake. Addtionally mainboard changes are done to support build. BUG=b:150217037 TEST=Build and boot waddledoo. Build jasperlake_rvp and volteer board. Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-03-26	mb/intel/jasperlake_rvp: add display related UPD configs	Ronak Kanabar
	Change-Id: Iad0b394dea017223a5b92fff0cb4c2ed1d5a7bd7 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39402 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24	mb/intel/jasperlake_rvp: Disable SATA controller	Usha P
	This patch disables the SATA config from devicetree for JSL RVP, since we are not planning to use the SATA storage in chrome config. Change-Id: I9cbcbf96e70b79bfb60f228b77a1065c26cd1aa2 Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-02-17	soc/intel/tigerlake: Enable Audio on TGL	Srinidhi N Kaushik
	Configure UPDs to support Audio enablement. Correct the upd name in jslrvp devicetree to avoid compilation issue. BUG=b:147436144 BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db Reviewed-on: https://review.coreboot.org/c/coreboot/+/38147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-02-15	mb/intel/jasperlake_rvp: Enable only required PCIE root ports	Usha P
	Jasper Lake SOC has 8 PCIe root ports. Cleaning up the root ports as per Jasper Lake. This patch updates the devicetree to enable WLAN and NVME for jasperlake_rvp and removes the other root port configurations which are not required. Change-Id: I6c801d81ccece6b45a7c45212533bb33a6805367 Signed-off-by: Usha P <usha.p@intel.com> Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38679 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18	soc/intel/tigerlake: Update chip files	Ravi Sarawadi
	Update chip files to include : - Update chip.c based on TGL FSP - Update chip.h based on TGL FSP - Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update - Update pmc_utils.c and JSL devicetree for build failure Reference PCH EDS#576591 vol1 rev1.2 BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37783 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18	mb/intel/jasperlake_rvp: Remove sd card detect gpio	Maulik V Vaghela
	Tigerlake SoC doesn't have GPIO defined for GPP_G. so compilation is failing due to this. We will update correct gpio for sd card detect once we have Jasper Lake soc gpio patch. partner bug for tracking: https://ticket.coreboot.org/issues/251 BUG=None BRANCH=NONE TEST='jslrvp' mainboard builds successfully Change-Id: I097b2f3a4fef1a487495a4aa9d2bcf88aa64f017 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-01-02	mb/intel/jasperlake_rvp: Add initial mainboard code	Aamir Bohra
	This is a initial mainboard code aimed to serve as base for further mainboard check-ins. This is a copy patch from icelake_rvp as on commit ID: I64db2460115f5fb35ca197b83440f8ee47470761 Below are the changes done over the copy patch: 1. Rename "Icelake" with "Jasperlake". 2. Replace "icelake_rvp" with "jasperlake_rvp". 3. Rename "icl" with "jsl". 4. Remove unwanted SPD file, add empty SPD as placeholder. 5. Replace "soc/intel/icelake" with "soc/intel/tigerlake" as tigerlake SOC hosts jasperlake code as well. 6. Empty romstage_fsp_params.c, to fill it later with SOC specific config. 7. Empty GPIO configuration, to be filled as per board. 8. Change copyright year to 2019. 9. Add two board support namely BOARD_INTEL_JASPERLAKE_RVP and BOARD_INTEL_JASPERLAKE_RVP_EXT_EC 10. Replace icl_u and icl_y variant with jslrvp variant. 11. Remove basebord gpio.c and rely on variant override. 12. Remove HDA verb table and config support. Changes to follow on top of this: 1. Add correct memory parameters, add SPDs. 2. Clean up devicetree as per jasperlake SOC. 3. Add GPIO support. 4. Update chromeos.fmd to make 10MB BIOS region. TEST=Build jasperlake rvp board Change-Id: I3314215807959b7348b71933fbba98e6487c0632 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>