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2010-08-30Restructured all vendors' Kconfig files to no longer source the boards'Jens Rottmann
Kconfigs from within the choice/endchoice block. This makes it possible to define user visible board specific options. Moved all vendor names and PCI ids to the vendors' Kconfigs. Now all options in each file depend on the same symbol, so replaced all "depends on"s with a single "if". Sorted boards (sort -d), cleaned whitespace. This patch also introduces a dummy option BOARD_SPECIFIC_OPTIONS, which is always "y" and never used. It it simply needed to have something to attach the boards' "select" statements to. Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-26Remove unused mainboard_config definitions. Trivial.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-07-06Re-integrate "USE_OPTION_TABLE" code.Edwin Beasant
Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com> Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-20Move generation of mptable entries for ISA to generic code.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5575 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-09Remove pc80/serial.c includes in ROMCC boards and includePatrick Georgi
it centrally in console/console.h instead. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-08Drop console/console.c and pc80/serial.c from mainboards'Patrick Georgi
romstage.c. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-05Rename "apic" and "apic_cluster" to "lapic" and "lapic_cluster"Patrick Georgi
in device trees. Adapt sconfig as necessary. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-27Since some people disapprove of white space cleanups mixed in regular commitsStefan Reinauer
while others dislike them being extra commits, let's clean them up once and for all for the existing code. If it's ugly, let it only be ugly once :-) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-25no warnings days.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5493 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-16zero warnings days: unify mp tables. fix warnings.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-14drop quite a lot of dead code that did nothing but produce warnings and makeStefan Reinauer
the rest of the code unreadable. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-09Drop the need for cpu_reset, it's really just a short cut to stage2.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-08Replace dual_core and quad_core CMOS (nvram) options with multi_core. Fix ↵Myles Watson
some white space. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-31Drop \r\n and \n\r as both print_XXX and printk now do this internally.Stefan Reinauer
Only some assembler files still have \r\n ... Can we move that part to C completely? Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-31This patch drops arch/i386/lib/console.c and arch/i386/lib/console_print.c andStefan Reinauer
makes include/console/console.h and console/console.c usable both in __PRE_RAM__ and coreboot_ram stages. While debugging this, I removed an indirection from the e7520 ram init code (same as we did on a couple of other chipsets, removes some register pressure from romcc) Also, drop remainders of CONFIG_USE_INIT (except the one odd piece of dead code in cache_as_ram.inc) Then some ap_romstage.c fixes, at least the nvidia/l1_2pvv compiled for me with CONFIG_AP_CODE_IN_CAR set in Kconfig which it did not before. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-30unify cmos.layout wrt AMD extended configuration registers.Stefan Reinauer
This removes double preprocessor define warnings from many boards. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5323 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-29This drops the ASSEMBLY define from romstage.c, tooStefan Reinauer
(since it's not assembly code, this was a dirty hack anyways) Also run awk 1 RS= ORS="\n\n" < $FILE > $FILE.nonewlines mv $FILE.nonewlines $FILE on romstage.c because my perl -pi -e 's,#define ASSEMBLY 1,,g' */*/romstage.c cut some holes into the source. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-29__PRE_RAM__ is now correctly specified in the Makefile. No need to hack it intoStefan Reinauer
romstage.c anymore Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-29This patch drops the coreboot CMOS checksum ranges from Kconfig becauseStefan Reinauer
the information is already specified in cmos.layout. coreboot is changed to use that version instead. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmai.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5313 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-28drop unneeded __ROMCC__ checks when the check for __PRE_RAM__ is moreStefan Reinauer
appropriate. Also, factor out post_code() for __PRE_RAM__ code and drop it from some mainboards. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-22Fix all the format string warnings.Myles Watson
Some other random warnings. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-22printk_foo -> printk(BIOS_FOO, ...)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-18Rework boolean expression (DeMorgan and all) forPatrick Georgi
better readability. Also remove failover.c files in mainboards, as they're not used anymore (and useless, too) Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-18Remove fallback/normal handling in mainboards'Patrick Georgi
romstage.c like r5255 did for failover/fallback/normal mainboards. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-27- make HAVE_HARD_RESET match what newconfig didPatrick Georgi
- introduce BOARD_HAS_HARD_RESET and use it if a board provides hard_reset in $(MAINBOARDDIR)/reset.c, instead of some chipset component - move a couple of rules out of the mainboards' Makefiles into src/arch/i386/Makefile.inc: initobj-y += crt0.o obj-y += mainboard.o obj-$(CONFIG_GENERATE_MP_TABLE) += mptable.o obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o obj-$(CONFIG_BOARD_HAS_HARD_RESET) += reset.o - remove Makefile.incs that are empty (or comment-only) after these changes, incl. Makefile.romccboard.inc (and references to it) - Make include not fail if Makefile.inc doesn't exist. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-27This does the following:Stefan Reinauer
cd coreboot/src/southbridge svn mv i82801ca i82801cx svn mv i82801dbm i82801dx svn mv i82801er i82801ex svn copy i82801xx i82801bx svn mv i82801xx i82801ax Plus, fixing up the filenames in these directories and the romstage.c and Kconfig files of the mainboards using those drivers. Plus, switching the thomson ip1000 and rca rm4100 to the i82801dx driver. There's a lot more to be done, like - adding device IDs for the ICH3 and newer drivers that have been kept in i82801xx so far - drop the additional parts support from the ax and bx drivers. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5167 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-09Move all the copies of the romstage.inc rule toPatrick Georgi
src/arch/i386/Makefile.inc For that to work, I had to: - Add a CONFIG_ROMCC variable - Set that variable on all ROMCC boards - conditionally choose romcc or gcc rule based on that variable - remove those two rules from all the boards' Makefiles - switch a couple of boards to HAVE_OPTION_TABLE, as they actually have. Also remove the duplication of rules with the sole difference of if they depend on option_table.h or not. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-08janitor task: unify and cleanup naming.Stefan Reinauer
cache_as_ram_auto.c and auto.c are both called "romstage.c" now. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-07newconfig is no more.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-25More Kconfig changes to improve match with newconfig:Patrick Georgi
DIMM_SUPPORT APIC_ID_OFFSET ACPI_SSDTX_NUM IRQ_SLOT_COUNT MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID (except msi/ms9185) MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID MEM_TRAIN_SEQ HAVE_ACPI_RESUME Also remove MMX (kconfig specific) and HAVE_MOVNTI and IOAPIC (which we deliberately differ in kconfig) from compareboard report. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-05* Explicitly add __PRE_RAM__ where it should be added.Stefan Reinauer
* Don't implicitly add __PRE_RAM__ in romcc. Fixes intel/xe7501devkit Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-27Make newconfig and kconfig agree on MAINBOARD_PCI_SUBSYSTEM_{VENDOR,DEVICE}_IDPatrick Georgi
Usually, this means adding values to Kconfig, but in a few cases, adding values to newconfig, too (which doesn't hurt). Also really hook up tyan/s2850 and tyan/s2875 to kconfig, and have them still build. Trivial and stupid kconfig changes, just lots of them. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-06Split the two usages of __ROMCC__:Myles Watson
__ROMCC__ now means "Don't use prototypes, since romcc doesn't support them." __PRE_RAM__ means "Use simpler versions of functions, and no device tree." There are probably some places where both are tested, but only one is needed. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24Major cleanups of the hard_reset() code and config in coreboot.- supermicro/x6dhe_g/auto.c
- Drop unused "#object reset.o" entries. - Use CONFIG_HAVE_HARD_RESET for all "object reset.o" entries. - Drop dead/commented code, i.e. useless hard_reset() from: - supermicro/x6dhe_g/auto.c - supermicro/x6dhe_g2/auto.c - supermicro/x6dhe_g2/auto.updated.c - supermicro/x6dhr_ig/auto.c - supermicro/x6dhr_ig2/auto.c - digitallogic/msm586seg/auto.c - dell/s1850/auto.c - Add "obj-$(CONFIG_HAVE_HARD_RESET) += reset.o" to kconfig files of boards that actually have a reset.c file. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4849 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-20Remove CONFIG_CPU_AMD_FAM10 & CONFIG_CPU_AMDK8 from mainboards. They should beMyles Watson
selected in sockets, and they aren't used yet. Add a couple of variables to src/Kconfig for lack of a better place so that their selects work. Add select statements according to newconfig for some variables that were defined but never selected in mainboard configs. Fix #if CONFIG_VGA==1 -> #if CONFIG_VGA. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4816 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17Move files from src/cpu/x86/{fpu,mmx,sse}/ to x86/Peter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16Drop enable_mmx.inc. It reads (only) "Enabling mmx registers is a noop"Peter Stuge
abuild tested Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16Set default ROM sizes per-board to match the ROM chip that cameUwe Hermann
with the respective board. Of course, the user can still override the size in menuconfig. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-15Add CONFIG_GENERATE_* for tables so that the user can select which tables notMyles Watson
to build, but by default all the tables that are available are built. Make PIRQ table build for qemu. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-09More Kconfig-supported boards, and also kconfig supportPatrick Georgi
for amd/socket_AM2R2, amd/socket_939, drivers/ati/ragexl Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07Major CONFIG_IRQ_TABLE_COUNT fixing and cleanups. Some of these boardsUwe Hermann
and PIRQ tables were actually wrong, I cannot imagine they ever worked properly. - Use CONFIG_IRQ_TABLE_COUNT in all irq_tables.c files instead of hard-coded numbers. - Make all CONFIG_IRQ_TABLE_COUNT values in irq_tables.c match Options.lb. - Make all CONFIG_IRQ_TABLE_COUNT values match the actual number of entries in the irq_tables.c file. - Set all CONFIG_IRQ_SLOT_COUNT values in src/.../Options.lb for those boards where they were set to 0 (in order to be overridden in the respective targets/.../Config.lb). This is mainly done to aid Patrick's scripts for kconfig conversion. - Fix a number of comments in irq_tables.c files. - Drop CONFIG_IRQ_SLOT_COUNT usage from boards that don't have irq_tables.c: - tyan/s1846 - asus/a8v-e_se - asus/m2v-mx_se Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07Fix intel board build on kconfig. MAX_CPUS was missingPatrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07More boards in kconfig, and moved -O2 flag for romcc intoPatrick Georgi
ROMCCFLAGS, so boards can override it where necessary. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-04This does away with CONFIG_ROM_PAYLOAD_START and CONFIG_PAYLOAD_SIZE.Patrick Georgi
Both were only really used in pre-cbfs, as the payload's size isn't relevant for the build process anymore. Various calculations in {no,}failovercalculation.lb are adapted accordingly. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-03Remove:Patrick Georgi
- CONFIG_CBFS - anything that's conditional on CONFIG_CBFS == 0 - files that were only included for CONFIG_CBFS == 0 In particular: - elfboot - stream boot code - mini-filo and filesystems (depends on stream boot code) After this commit, there is no way to build an image that is not using CBFS anymore. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-03Remove duplicate and not too useful Kconfig board comments asUwe Hermann
per discussion on the mailing list. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-29Fix a number of board names in Kconfig (trivial).Uwe Hermann
Also, simplify the M2V-MX SE Kconfig file a bit while I'm at it. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4688 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-25some progress on kconfig:Patrick Georgi
- northbridges are done - southbridges are done - Intel CPUs are done, with a design that the board only has to specify the socket it has, and the CPUs are pulled in automatically. There is some more cleanup possible in that area, but I'll do that later - a couple more mainboards compile: - intel/eagleheights - intel/jarrell - intel/mtarvon - intel/truxton - intel/xe7501devkit - sunw/ultra40 - supermicro/h8dme - tyan/s2850 - tyan/s2875 - via/epia - via/epia-cn - via/epia-m - via/epia-m700 - via/epia-n - via/pc2500e (PPC not considered, probably overlooked something) All of them only _build_, but some options are probably completely wrong. To be fixed later Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-23simplify source tree hierarchy: move files from sdram/ and ram/ to lib/Stefan Reinauer
It's only three files. Also fix up all the paths (Gotta love included C files) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12Kconfig!Patrick Georgi
Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> tested on abuild only. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-11Enable CBFS everywhere. All boards compiled for me (abuild tested),Patrick Georgi
and we will fix issues as they appear. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-30the tool chain settings should not be in renamed (as they will never live inStefan Reinauer
Kconfig) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-30This patch unifies the use of config options in v2 to all start with CONFIG_Stefan Reinauer
It's basically done with the following script and some manual fixup: VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC` for VAR in $VARS; do find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \; done Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-19Undo my ugly commit that added uses clauses in lots of places instead of one.Myles Watson
Fix configuration of all boards. (Abuild tested) Hopefully fix compilation of PPC boards (they've never compiled for me.) Apologize profusely. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-17Fix configuration of boards that didn't have uses CONFIG_USE_INIT. Trivial.Myles Watson
Abuild tested with -C. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-06When I started refactoring mainboard Config.lb, I added two differentCarl-Daniel Hailfinger
files for targets without failover: src/config/nofailovercalculation.lb (64 kB XIP) src/config/nofailovercalculation128.lb (128 kB XIP) Targets with other XIP sizes were ignored. This patch moves XIP size back into mainboard code. Benefits from this patch: - src/config/nofailovercalculation128.lb is no longer needed - Targets with XIP sizes besides 64k and 128k benefit from refactoring - Conceptually, this makes the include files pure calculation files without settings. Abuild tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-03Revert "CMOS: Add set_option and rework get_option."Luc Verhaegen
This reverts commit eb7bb49eb5b48c39baf7a256b7c74e23e3da5660. Stepan pointed out that "s" means string, which makes the following statement in this commit message invalid: "Since we either have reserved space (which we shouldn't do anything with in these two functions), an enum or a hexadecimal value, unsigned int seemed like the way to go." Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Luc Verhaegen <libv@skynet.be> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-03CMOS: Add set_option and rework get_option.Luc Verhaegen
To ease some of my debugging pain on the unichrome, i decided i needed to move FB size selection into cmos, so i could test a size and then reset it to the default after loading this value so that the next reboot uses the (working) default again. This meant implementing set_option in parallel to get_option. get_option was then found to have inversed argument ordering (like outb) and passing char * and then depending on the cmos layout length, which made me feel quite uncomfortable. Since we either have reserved space (which we shouldn't do anything with in these two functions), an enum or a hexadecimal value, unsigned int seemed like the way to go. So all users of get_option now have their arguments inversed and switched from using ints to unsigned ints now. The way get_cmos_value was implemented forced us to not overlap byte and to have multibyte values be byte aligned. This logic is now adapted to do a full uint32_t read (when needed) at any offset and any length up to 32, and the shifting all happens inside an uint32_t as well. set_cmos_value was implemented similarly. Both routines have been extensively tested in a quick separate little program as it is not easy to get this stuff right. build_opt_tbl.c was altered to function correctly within these new parameters. The enum value retrieval has been changed strol(..., NULL, 10) to stroul(..., NULL, 0), so that we not only are able to use unsigned ints now but so that we also interprete hex values correctly. The 32bit limit gets imposed on all entries not marked reserved, an unused "user_data" field that appeared in a lot of cmos.layouts has been changed to reserved as well. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22Convert 12 more boards to use include statements in Config.lb.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4186 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22no duplicate names in cmos.layout allowed. (fixes a bunch of boards)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4175 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22This patch unifies the socket_mPGA604_800Mhz and socket_mPGA604_533Mhz to aStefan Reinauer
combined socket_mPGA604. No other sockets come with clock rates, and there is no difference in code, except for the number of microcode patches included in a build. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4169 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-14v2/src romfs->cbfs renamePeter Stuge
This also has the config tool changes in v2/util. Rename romfs.[ch]->cbfs.[ch] and sed romfs->cbfs romtool->cbfstool ROMFS->CBFS Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-31Add the CONFIG_ROMS config variable. Ronald G. Minnich
Tested under abuild, causes no trouble. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-13This, ladies and gentlement, is commit #4000.Stefan Reinauer
Use the (almost) same strict CFLAGS in v2 that we use on v3. And fix a few include files and missing prototypes. Also, fix up the Config-abuild.lb files to properly work for cross compiling. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-18Carl-Daniel's part:Carl-Daniel Hailfinger
This patch converts mainboard_$VENDOR_$BOARD_ops to mainboard_ops and mainboard_$VENDOR_$BOARD_config to mainboard_config. Ron's part: The config change that makes the naming change not break every build. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-22Fix implicit declarations of pci_read_config8 and pci_write_config8 inCarl-Daniel Hailfinger
the following files: src/mainboard/intel/jarrell/reset.c src/mainboard/supermicro/x6dai_g/reset.c src/mainboard/supermicro/x6dhe_g2/reset.c src/mainboard/supermicro/x6dhe_g/reset.c src/mainboard/supermicro/x6dhr_ig2/reset.c src/mainboard/supermicro/x6dhr_ig/reset.c Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3832 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-01The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots ofCarl-Daniel Hailfinger
code to use it. That makes the code more readable and also less error-prone. Abuild tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-04This changes the python generated makefilesCarl-Daniel Hailfinger
targets/*/*/Makefile targets/*/*/normal/Makefile targets/*/*/fallback/Makefile to use a common copy of romcc, and to leave this compiler untouched by 'make clean' in targets/*/*/fallback/ and targets/*/*/normal/ . 'make clean' in targets/*/*/ will clean romcc. Thanks to Mats for the initial idea and implementation of a tool to do this. This patch has almost the same behaviour as the original tool without having to run the tool each time. Tested for abuild-friendliness. The patch saves ~10-12 seconds for every target using romcc. For a full abuild run, this is ~20% time saved. For the first 38 abuild targets, total build time is down to 13m24s instead of 16m22s on my machine. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Mats Erik Andersson <mats.andersson@gisladisker.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18Rename almost all occurences of LinuxBIOS to coreboot. Stefan Reinauer
Due to the automatic nature of this update, I am self-acking. It worked in abuild. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-30The following mainboards had a file named microcode_updates.c in theirCarl-Daniel Hailfinger
mainboard directories, but the code was not referenced anywhere. intel/jarrell dell/s1850 supermicro/x6dhr_ig2 supermicro/x6dhr_ig supermicro/x6dhe_g2 supermicro/x6dhe_g Besides that, the contents of these files were either duplicates of src/cpu/intel/model_f3x/microcode_M1DF340E.h or src/cpu/intel/model_f3x/microcode_M1DF3413.h. svn remove the following files: src/mainboard/supermicro/x6dhe_g/microcode_updates.c src/mainboard/supermicro/x6dhe_g2/microcode_updates.c src/mainboard/supermicro/x6dhr_ig/microcode_updates.c src/mainboard/supermicro/x6dhr_ig2/microcode_updates.c src/mainboard/dell/s1850/microcode_updates.c src/mainboard/intel/jarrell/microcode_updates.c Abuild tested, as expected no failures. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-09This adds the same line (uses CONFIG_PRECOMPRESSED_PAYLOAD) to everyMyles Watson
Options.lb file that already had a "uses CONFIG_COMPRESSED_PAYLOAD_LZMA" line in it. I figure that only adding it to the files that already have support for LZMA payloads makes sure I don't break anything. Signed-off-by: Myles Watson <myles@pel.cs.byu.edu> Acked-by: Ward Vandewege <ward@gnu.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3002 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-04Restructure the PCI IDs list for the ICH* chipsets from ICH/ICH0 up toUwe Hermann
ICH5/ICH5R (more to follow) in preparation of further 82801xx improvements. Use human-readable names for the PCI ID #defines. Rename *_ISA to *_LPC as per datasheet. The 82801DBM only has 3 (not 4) USB devices, looks like a copy-paste error. The fixes in southbridge code are only to keep the build working for now, any real improvements will only go into the 82801xx code in future. This is abuild-tested so it shouldn't break anything. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2938 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-15Apply linuxbios-rename-other-payload-options.patchEd Swierk
(Patch 2, refs #14) Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2529 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-15Apply linuxbios-rename-compressed-payload-options.patch, refs #14Ed Swierk
Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2527 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-10* fix the automatic build system by compressing payloads if possibleStefan Reinauer
and leaving enough room for a real payload (not /dev/null) This is a wonderful example why "uses" sucks. * add Config-abuild.lb for those boards that dont build with the default settings and a real payload: arima/hdama, amd/quartet, amd/serengeti_cheetah, ibm/e326 * if lzma is installed and a real payload is used, try compressing it. * fix a small bug in "abuild --help" This patch is acked by me because its due to infrastructural changes only. Flames welcome. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-05Use the canonical name of the vendors/devices and theUwe Hermann
same format for all CHIP_NAME() entries in LinuxBIOS (Closes #20). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@linuxbios.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-02Remove some unneeded #includes from most mainboard.c files.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-27Rename E7520 to e7520, and E7525 to e7525 in the code. The next commitUwe Hermann
will then rename the E7520 and E7525 directories respectively. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2477 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-27Fix the CHIP_NAME() entries of all mainboards to have the same formatUwe Hermann
and (hopefully) the correct canonical name of the vendor and board. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2476 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-24Change all occurences of NSC to nsc in the code. The next commitUwe Hermann
will then rename the src/superio/NSC directory to src/superio/nsc. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2472 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-06break the tree really quick due to svn restrictions, next commit fill fix itStefan Reinauer
again. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-11-27fix intel jarrell build (no issue tracker number since trivial fix)Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-08eric patchYinghai Lu
1. x86_setup_mtrr take address bit. 2. generic ht, pcix, pcie beidge... 3. scan bus and reset_bus 4. ht read ctrl to decide if the ht chain is ready 5. Intel e7520 and e7525 support 6. new ich5r support 7. intel sb 6300 support. yhlu patch 1. split x86_setup_mtrrs to fixed and var 2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource 3. in_conherent.c K8_SCAN_PCI_BUS git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-02 16:33:12 +0000