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This implementation adds below changes:
1. Add chrome ec asl support for iclrvp.
2. EC SCI, SMI, S3/S5 wake events.
3. Wake pin and EC SMI GPE confiiguration.
Change-Id: Ie95da92f7125e56fe9ef9d57a1098278c308918e
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/29797
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This implementation updates the GPIO pins, communities and
group mapping.
Change details:
1. Update 5 GPIO community includes 11 GPIO groups
GPIO COM 0
GPP_G, GPP_B, GPP_A
GPIO COM 1
GPP_H, GPP_D, GPP_F
GPIO COM 2
GPD
GPIO COM 4
GPP_C, GPP_E
GPIO COM 5
GPP_R, GPP_S
2. Update GPIO IRQ routing.
3. Add GPIO configuration for iclrvp board.
Change-Id: I223abacc18f78631a42f340952f13d45fa9a4703
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Clone entirely from mainboard/intel/cannonlake_rvp
commit id: af89f49b83260a04dece84b34e97560fb85d29ae
List of changes on top off initial cannonlake_rvp clone
1. Rename "Cannonlake" with "Icelake".
2. Replace "cannonlake_rvp" with "icelake_rvp".
3. Rename "cnl" with "icl".
4. Remove unwanted SPD file, will add correct SPD with mainboard
patches.
5. Remove NHLT related implementation.
6. Remove FSP configs, will add once FSP headers are available.
7. Removed smihandler.c, will add later if needed.
Change-Id: I875972d1fb2f630bf5eb29bd955c484e7f9aa415
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29164
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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