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Objects that are created with acpigen need to be declared
with External () for the generation of dsdt.asl to pass
iasl without errors.
There are some objects that are common to all platforms,
and some that should be declared only conditionally.
Having a top-level ASL helps to achieve this.
Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I306f8cd74af62c0cd30f445d20c47f774f122481
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49247
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.
Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).
Change-Id: I80369ab70d5510cb4f388f3029119e7148361af4
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49435
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Do LPC/eSPI pad configuration at board-level to match other platforms.
This is done by adding one missing pad to the early gpio table and
dropping the call to the soc function.
The soc code gets dropped in CB:49410.
Change-Id: I210633d4520fcfab59f68268bd7991557433ce38
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49415
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently the decision of whether or not to use mrc_cache in recovery
mode is made within the individual platforms' drivers (ie: fsp2.0,
fsp1.1, etc.). As this is not platform specific, but uses common
vboot infrastructure, the code can be unified and moved into
mrc_cache. The conditions are as follows:
1. If HAS_RECOVERY_MRC_CACHE, use mrc_cache data (unless retrain
switch is true)
2. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_BOOTBLOCK, this
means that memory training will occur after verified boot,
meaning that mrc_cache will be filled with data from executing
RW code. So in this case, we never want to use the training
data in the mrc_cache for recovery mode.
3. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_ROMSTAGE, this
means that memory training happens before verfied boot, meaning
that the mrc_cache data is generated by RO code, so it is safe
to use for a recovery boot.
4. Any platform that does not use vboot should be unaffected.
Additionally, we have removed the
MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config because the
mrc_cache driver takes care of invalidating the mrc_cache data for
normal mode. If the platform:
1. !HAS_RECOVERY_MRC_CACHE, always invalidate mrc_cache data
2. HAS_RECOVERY_MRC_CACHE, only invalidate if retrain switch is set
BUG=b:150502246
BRANCH=None
TEST=1. run dut-control power_state:rec_force_mrc twice on lazor
ensure that memory retraining happens both times
run dut-control power_state:rec twice on lazor
ensure that memory retraining happens only first time
2. remove HAS_RECOVERY_MRC_CACHE from lazor Kconfig
boot twice to ensure caching of memory training occurred
on each boot.
Change-Id: I3875a7b4a4ba3c1aa8a3c1507b3993036a7155fc
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46855
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Both Gemini Lake boards in the tree use the same value.
Change-Id: Ib6bd05206026736fd7e3d44b49e4d8ba217c2708
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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For consistency with other platforms, use `SOC_INTEL_GEMINILAKE`.
Change-Id: I06310e5a9bca6c9504f19a6c2fe9b26626f290d4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Found using:
diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX' -- src/) |grep -v vendorcode |grep '<'
Change-Id: I5e14bf4887c7d2644a64f4d58c6d8763eb74d2ed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41827
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I6948a0b9a6b699cb44e3e02d9e134180bac2fa14
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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Update processor power limit configuration parameters based on
common code base support for Intel Apollo Lake SoC based platforms.
BRANCH=None
BUG=None
TEST=Built and tested on octopus system
Change-Id: I609744d165a53c8f91e42a67da1b972de00076a5
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41233
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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.write_acpi_tables() should not be updating the device structure. This
change makes the struct device * argument to it as const.
Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I1ea2eebfdd43610e42b4cf04409ec76c2e8b0042
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These two identifiers were always very confusing. We're not filling and
injecting generators. We are filling SSDTs and injecting into the DSDT.
So drop the `_generator` suffix. Hopefully, this also makes ACPI look a
little less scary.
Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: David Guckian
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add HID field in max98357a_config and allow mainboards to set it.
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I22d2d078a9a4eb6ab330da8439737ff5133086d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39286
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I426518e8e18de1c8efcfb7ecb0835df3e257dca1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39608
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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wpsw_boot is deprecated in favour of wpsw_cur. As such,
coreboot no longer needs to share "write protect" GPIO
with depthcharge.
BUG=b:124141368, chromium:950273
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I2fcb7f82aa063fd72928171af5cbef0356ba620c
Signed-off-by: Joel Kitching <kitching@google.com>
Cq-Depend: chromium:2088434
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39318
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested with BUILD_TIMELESS, no changes.
Change-Id: Iaf615e95a30e9c02ad49351a3c0db253ad713ad4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Due to build rules, dummy acpi_tables source files were added in many
mainboards. With commit 1e83e5c61a3aa98f58f7d8cbf8d1eb9532896cc3
("src/arch/x86: Build mainboard acpi_tables source if present"),
the build system will build mainboard acpi_tables only if present. Remove
the dummy/empty/blank acpi_tables source files.
BUG=None
TEST=Build test with some google mainboards.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0cef34368e2e5f5e3b946b22658ca10c7caad90a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Previously, each Intel chipset had its own sleepstates.asl file.
However, this is no longer the case, so drop these comments.
Change-Id: I50aba6e74f41e2fa498375b5eb6b7e993d06bcac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Kconfig became stricter on what it accepts, so accomodate before
updating to a new release.
Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The devicetree is not made for user-choosable options, thus introduce
Kconfig options for both SGX and the corresponding PRMRR size.
The PRMRR size Kconfig has been implemented as a maximum value. At
runtime the final PRMRR size gets selected by checking the supported
values in MSR_PRMRR_VALID_CONFIG and trying to select the value nearest
to the chosen one.
When "Maximum" is chosen, the highest possibly value from the MSR gets
used. When a too strict limit is set, coreboot will die, printing an
error message.
Tested successfully on X11SSM-F
Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch creates a common instance of sleepstates.asl inside intel common
code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to
refer sleepstates.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
S0/S3/S4/S5 entries after booting to OS.
Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Previously all boards using eSPI for the Chrome EC just called it
LPC as the code for the chrome EC is the same between the two
busses.
I'm adding a new Kconfig symbol to specify eSPI, so switch the
boards that actually use eSPI to that symbol and add the LPC
symbol to all the others.
The EC_GOOGLE_CHROMEEC_LPC symbol will no longer default
to enabled for x86 platforms, so one symbol or the other needs to be
specified for each platform.
BUG=b:140055300
TEST=Build tested only.
Change-Id: Icf242ca2b7d8b1470feda4e44b47a2cdc20680f2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The CONFIG_GBB_HWID can be generated automatically now so we can remove
the test-only HWIDs set in board config files.
BUG=b:140067412
TEST=Built few boards (kukui, cheza, octopus) and checked HWID:
futility gbb -g coreboot.rom
Change-Id: I4070f09d29c5601dff1587fed8c60714eb2558b7
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35635
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These are required to cover the absensce of .data and
.bss sections in some programs, most notably ARCH_X86
in execute-in-place with cache-as-ram.
Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Build of the entire smm-class is skipped if we have
HAVE_SMI_HANDLER=n.
Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The gpio table is only used by depthcharge, and depthcharge rarely
has a need for the "recovery" gpio. On a few boards it does use the
gpio as a signal for confirming physical presence, so on that boards
we'll advertise the board as "presence".
All these strings probably should have been #defines to help avoid
typos (e.g., the "ec_in_rw" in stout seems questionable since everybody
else uses "EC in RW").
Cq-Depend: chromium:1580454
BUG=b:129471321
BRANCH=None
TEST=Local compile and flash (with corresponding changes to depthcharge)
to 2 systems, one with a "presence" gpio and another without. Confirmed
that both systems could enter dev mode.
Change-Id: Id6d62d9e48d3e6646cbc1277ea53f0ca95dd849e
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Currently only two devices make use of physical dev switch:
stumpy, lumpy
Deprecate this switch. If these devices are flashed to ToT,
they may still make use of virtual dev switch, activated
via recovery screen.
BUG=b:124141368, b:124192753, chromium:942901
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I87ec0db6148c1727b95475d94e3e3f6e7ec83193
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31943
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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For Chrome OS (or vboot), The PRESERVE flags should be applied on
following sections:
RO_PRESERVE, RO_VPD, RW_PRESERVE, RW_ELOG, RW_NVRAM, RW_SMMSTORE,
RW_VPD, RO_FSG (b:116326638), SI_GBE (chromium:936768),
SI_PDR (chromium:936768)
With the new PRESERVE flag, we don't need RO_PRESERVE and RW_PRESERVE in
the future. But it's still no harm to use it if there are multiple
sections all needing to be preserved.
BUG=chromium:936768
TEST=Builds google/eve and google/kukui inside Chrome OS source tree.
Also boots successfully on eve and kukui devices.
Change-Id: I6664ae3d955001ed14374e2788d400ba5fb9b7f8
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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These are completely throwing Kconfig off, resulting in duplicate
entries.
Change-Id: I401467da686d5011a456b661a10170492a919c81
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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These pins should not have pull downs configured in standby state as that
can cause contention on the termination circuitry and lead to incorrect
behavior as per Doc# 572688 Gemini Lake Processor GPIO Termination
Configuration.
BUG=b:79982669
TEST=Checked that code compiles with changes.
Change-Id: I8156c67df152555ecf9e7be9e4851468538bcff1
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/c/30867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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|
Does not fix 3rdparty/, *.S or *.ld or yet.
Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/17656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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After f5ca922 (Untangle CBFS microcode updates) got merged, all
mainboard using intel apollolake, cannonlake, coffeelake, glk,
kabylake, skylake, icelake and whiskeylake get affected.
Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG
and set default console for each platform.
BUG=N/A
TEST=Build and test on Sarien platform, by default we can still get
console from cbmem, and enable CONSOLE_SERIAL can get logs from UART
port 2.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de
Reviewed-on: https://review.coreboot.org/c/30853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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|
Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: David Guckian
|
|
Field 'OEMID' & "OEM Table ID" are related to DSDT table
not to mainboard.
So use macro to set them respectvely to "COREv4" and
"COREBOOT".
Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
|
|
DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version.
This will cause the AML interpreter to use 32-bit integers and math
if the version is 1, and 64-bit if the version is >=2.
Current spec version is 2 for ACPI 6.2-a.
Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29626
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The helper function to get the board version from EC returns 0 on
failure. But 0 is also a valid board version. Update the helper function
to return -1 on failure and update the use-cases.
BUG=b:114001972,b:114677884,b:114677887
Change-Id: I93e8dbce2ff26e76504b132055985f53cbf07d31
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/28576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>
|
|
Only for those that are x86 and also have a RW_LEGACY region.
The assumption is that all devices touched have 64k block sizes when
choosing size and alignment of the region.
Change-Id: I12addb137604f003d1296f34f555dae219330b18
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: Ief6a04ccb63658b5fb03cd1d298bf00948cf7410
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Until now, chromeec was doing keyboard initialization for the boards
that have DRIVERS_PS2_KEYBOARD selected. However, coreboot does not
leave the keyboard controller in a default reset state. This could
result in payloads or OS failing to probe the controller as there
could be stale data buffered in the controller during the handoff.
Since the boards using chromeec already perform keyboard
initialization in payload, there is no need to initialize the
keyboard in coreboot too. This change gets rid of DRIVERS_PS2_KEYBOARD
selection from all google mainboards using chromeec.
BUG=b:110024487
Change-Id: I9af48e648231c18f98d0cc1ddd178b8d00082b0a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This pin does not have a native function for eSPI. Nonetheless if we use
eSPI, it should be configured as a GPIO and kept unconnected to allow
S0ix entry.
Also removed initialization of LPC pins in mainboard code as they are
already initialized in chipset code. The settings fpr LPC pins in
chipset code were updated to those that were previously in mainboard
code and have been validated on LPC flavor of Geminilake RVP.
BUG=b:79251613
BRANCH=none
TEST=From kernel prompt in bip, type powerd_dbus_suspend.
Check on EC console that SOC enters S0ix.
Change-Id: Ie0c1013fee638a3b7a91469736efc0c25a1597fa
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/23742
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Adding common chip config structure which will be used to return data to
common code. When common code requires soc data, code used to fetch
entire soc config structure. With this change, common code will only get
the data/structure which is required by common code and not entire
config.
For now, adding i2c, gspi and lockdown configuration which will be used
by common code.
BUG=none
BRANCH=b:78109109
TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check
values are returned properly using common structure.
Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26189
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
* Remove 2nd software stack in pc80 drivers directory.
* Create TSPI interface for common usage.
* Refactor TSS / TIS code base.
* Add vendor tss (Cr50) directory.
* Change kconfig options for TPM to TPM1.
* Add user / board configuration with:
* MAINBOARD_HAS_*_TPM # * BUS driver
* MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2
* Add kconfig TPM user selection (e.g. pluggable TPMs)
* Fix existing headers and function calls.
* Fix vboot for interface usage and antirollback mode.
Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
GeminiLake platform is fan-less design. We do not need these DPTF_CPU_ACTIVE_ACx
defines. Removing these for GeminiLake RVP board as these are not being used.
Change-Id: I810809bf58198a028e6cfcdbd68887f5f154a0ad
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/26469
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use of device_t has been abandoned in ramstage.
Change-Id: I791a69aeca9b44daabc9a3e5fb9ac92e6b22f3e5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Instead of writing out '__attribute__((weak))' use a shorter form.
Change-Id: If418a1d55052780077febd2d8f2089021f414b91
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
When building with Intel EC selected, unselect Chrome EC specific
options i.e., LID switch to prevent build error.
BUG=None
BRANCH=None
TEST=Build with Intel EC selected, Build should be successful.
Change-Id: I39d6d65bbfd08d684af43972b89ca78fcbd58567
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/25479
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This enables ThunderPeak WiFi card on M.2.
TEST=Verify wlan card shows up in lspci
Change-Id: I5b3f871bdc67bfc4ed283b997b2a5698451b2bd2
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/24931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch sets the PNP config value to PNP_PERF_POWER.
The config values for soc can be found in chip.h
TEST = Built and booted glkrvp, verified warm and cold
reboot and suspend resume.
Change-Id: Ia390c0fafe2de64bd9e4ca44e5ed5d904663ae3c
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/25309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Update the size in WP_RO segment of the flash to accommodate builds using
debug FSP.
Change-Id: I8b24422e1eef2d0a81006286d4fc58f238fdce11
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/25255
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ#
from mainboards instead of defining a separate property for each root
port. This allows us to use memcpy to copy the entire array into FSP
params as well as new properties for PCIe root ports can be added as
arrays in future CLs.
BUG=b:74633273
BRANCH=reef,coral
Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Read cse file was not getting cached and taking about 500ms on every boot.
Change-Id: I8c92eefc64fe146c628d9c104d7dfb016204004c
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/23743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Enable S0ix wake mask programming from coreboot using unified host event
programming interface.
BRANCH=none
BUG=none
TEST=Verify masks with ec hostevent command on S0, S3, S5 and S0ix. Also
check that lidclose/lidopen command from EC console wakes system up from
S3 or S0ix.
Change-Id: I60343aaa9e0ddfd38d42b6d0aa2820e2fd880fb7
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/23453
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add config option SOC_ESPI in glkrvp Kconfig. This is to disable LPC
and enable eSPI instead.
TEST=Boot to OS
Change-Id: I3116b656d41d1d7719c254888d1e3640628a97ca
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
Audio DMIC_DATA needs to be ON in S0ix to support Wake on Voice.
By doing this, SoC can see the DMIC DATA and use for WoV processing.
Thus configuring GPIO_173 as IGNORE IOSSTATE.
TEST=put DUT in S0ix, verify DUT wakes up
Change-Id: I8bf403564e927deb8fed7f415e334bb230107cb0
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/23246
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch adds the EC_GOOGLE_CHROMEEC_SWITCHES option so that we
use the common switch.c file
Change-Id: I93a2ba63015db17989c89ce1b5897de6a93e201f
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/23131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This patch adds recovery cache.
TEST:glkrvp boots with this change and also FAFT test
firmware_CorruptRecoveryCache passes.
Change-Id: I9b32628d814693fb0591fc3750348d48cf9e26f1
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/23067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This patch configures the EC_SCI_GPI when ESPI is enabled.Also adds
mainboard espi handler function.
TEST= Boot to OS and SMI/SCI is working when ESPI is enabled/disabled.
Change-Id: I2b3845d54ad7c1f14edc86f71b3f968424711999
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Configure PRMRR to allocate 128MiB for SGX enclave memory and enable SGX
by default for GLKRVP platform.
Supported PRMRR size options:
0x02000000 - 32MiB
0x04000000 - 64MiB
0x08000000 - 128MiB
Change-Id: Ifa39df4a1da84bae49551a9626257bda0729752b
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch enables the APLS touchpad in glkrvp platform.
TEST= Boot and test touchpad works.
Change-Id: I6f52f7db57ab52b5531e647bde2adbb78b40f76f
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22627
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Add proper variants gpio.h in dsdt.asl where the GPE_EC_WAKE and
EC_SCI_GPI is defined.
Change-Id: Ideb6dd4d0ac496a81721cd883865218cb19583d9
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
On GLK EC does not support temperature reads and does not control
the fans anymore, OS is responsible fan control through EC.
This hack enables running of the fan for boards without External EC.
Change-Id: I361e53d4fd53678f3abb8fe9862071aec6e149a7
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/22235
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
This patch does not put CLKRUN in IOSTANDBY.
Change-Id: I7fedd729d3bb66c2b52a63166e461f8760457721
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Skip LPC related gpio configuration if eSPI config option
is selected.
Change-Id: I15c5f769f36a1801217b1e3650379c7b181d814f
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22757
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Audio DMIC_CLK needs to be ON in S0ix to support Wake on Voice.
So, configuring GPIO_171 to be as IGNORE IOSSTATE, so that
clock is ON in S0ix state.
BUG=None
TEST=put DUT in S0ix, verified DMIC_CLK
in scope when wov capture path is ON
Change-Id: I147cf3c12acb11429c6cb234e8c511f57886b6b4
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/22675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Merge the different coreboot table strapping ID structures into one
because they're really just all the same, and I want to add more. Make
the signature of the board_id() function return a uint32_t because
that's also what goes in the coreboot table. Add a printk to the generic
code handling strapping IDs in ramstage so that not every individual
mainboard implementation needs its own print. (In turn, remove one such
print from fsp1_1 code because it's in the way of my next patch.)
Change-Id: Ib9563edf07b623a586a4dc168fe357564c5e68b5
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
SCI trigger logic had to be inverted.
This patch enables the system to wake up from S3 when lid is opened
when the system is in suspend state.We are trying to match what a
external EC card running ChromeEC FW is sending on the signal.
TEST = Verified that system wakes up from S3 on toggling lid switch
back to open state.
Change-Id: Ib42a38088ee028eddc6769921b0552c569da25a9
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I513b26d39973d9714b531d1ab0755c66d19eb332
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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mainboard_ec_init implemented by all x86-based mainboards using
chromeec performed similar tasks for initializing and recording ec
events. Instead of duplicating this code across multiple boards,
provide a library function google_chromeec_events_init that can be
called by mainboard with appropriate inputs to perform the required
actions.
This change also adds a new structure google_chromeec_event_info to
allow mainboards to provide information required by the library
function to handle different event masks.
Also, google_chromeec_log_device_events and google_chromeec_log_events
no longer need to be exported.
Change-Id: I1cbc24e3e1a31aed35d8527f90ed16ed15ccaa86
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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This patch adds the below:
1) Add correct SSP endpoint config for spk and headset
2) Update GPIO config for jack detection
3) Update GPIO config for I2S pins
TEST=sound card binds
TEST=cross checked SSDT entries from
/sys/firmware/acpi/tables/
TEST=Jack interrupt works
Change-Id: I32022ddacd79917730080889c040f842e0c9e6b9
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/19799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add LPC common code to be shared across Intel platforms.
Also add LPC library functions to be shared across platforms.
Use common LPC code for Apollo Lake soc. Update existing Apollolake
mainboard variants {google,intel,siemens} to use new common
LPC header file.
Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/20659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Updating the common smihandler to handler gpi events which
originally were going to be left to each soc to handle. After
some more analysis the gpi handler can also be commonized.
Change-Id: I6273fe846587137938bbcffa3a92736b91982574
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/20917
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Sets RAPL PL1 power to ~6W.
Note: 7.5W setting gives a run-time 6W actual measured power.
Tested on GLK w/kernel 4.11.0 by reading MSR 0x610 at runtime
and comparing to measured power on an instrumented board.
Change-Id: I07caeb2895a579387025d3b0fb7f1d2c3d5e2665
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/19746
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GLKRVP is a reference board for GLK SOC
RVP1 has DDR4 and RVP2 has LPDDR4
RVP2 is enabled by default and CONFIG_IS_GLK_RVP_1 should be selected
if building for RVP1
GLKRVP can work with internal Intel EC or external Chrome EC AIC.
For internal EC, CONFIG_EC_GOOGLE_CHROMEEC will not be selected (
CONFIG_GLK_INTEL_EC should be selected for internal EC config)
By default, CONFIG_GLK_CHROME_EC is selected for external ChromeEC AIC
config.
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: Iab688aca6a4f5c5e32801215ba3a1a440e50fbef
Reviewed-on: https://review.coreboot.org/19604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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