coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2016-09-30	mainboard/intel/quark: Add FSP selection values	Lee Leahy
	Add Kconfig values to select the FSP setup: * FSP version: 1.1 or 2.0 * Implementation: Subroutine or SEC/PEI core based * Build type: DEBUG or RELEASE * Enable all debugging for FSP * Remove USE_FSP1_1 and USE_FSP2_0 Look for include files in vendorcode/intel/fsp/fsp???/quark BRANCH=none BUG=None TEST=Build FSP 1.1 (subroutine) and run on Galileo Gen2 Change-Id: I3a6cb571021611820263a8cbfe83e69278f50a21 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/16806 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-05	soc/intel/quark: Add FSP 2.0 boot block support	Lee Leahy
	Add the pieces necessary to successfully build and run bootblock using the FSP 2.0 build. TEST=Build and run bootblock on Galileo Gen2 Change-Id: I2377f0b0147196f100396b8cd7eaca8f92d6932f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15865 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-11	mainboard/intel/galileo: Support bootblock in C	Lee Leahy
	Initialize the GPIOs during the boot block to properly route the SOC UART pins. TEST=Build and run on Galileo Gen2 Change-Id: I22c24f8c83f04566a0bbd598a141a5209569a924 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/15133 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-31	mainboard/intel/quark: Enable reg_access during romstage	Lee Leahy
	Turn on reg_access during romstage. TEST=Build and run on Galileo Gen2 Change-Id: Iff1616836d6031f43d7741693febefa0bf26b948 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15008 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31	mainboard/intel/galileo: Split out enabling FSP1_1	Lee Leahy
	Split out enabling FSP 1.1 support to prepare for enabling FSP 2.0 support. TEST=Build and run on Galileo Gen2. Change-Id: Ic4e814bcf61f9480f98e2d7bc7a1648dec43a07d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15001 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-18	mainboard/intel/galileo: Add I2C chip initialization	Lee Leahy
	Add I2C chip initialization for the Galileo boards. TEST=Build and run on Galileo Gen2 Change-Id: Ib5284d5cd7a67de2f3f98940837ceb2aa69af468 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14829 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17	mainboard/intel/galileo: Add GPIO initialization	Lee Leahy
	Add Kconfig to configure coreboot for a specific Galileo board. Configure the GPIOs for the specific Galileo board. TEST=Build and run on Galileo Gen2 Change-Id: I992460d506b5543915c27f6a531da4b1a53d6505 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14826 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04	mainboard/intel/galileo: Add Intel Galileo Gen 2 Support	Lee Leahy
	Add the files to build soc/intel/quark and mainboard/intel/galileo for a minimal coreboot image. Please note that this configuration does not run. Include HTML documentation for the Galileo Gen 2 board. Testing is successful if build completes successfully. TEST=Build for Galileo Change-Id: Idd3fda1b8ed9460fa8c92e6dcaa601c3c9f63a36 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13507 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>