coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2012-11-13	Make EmeraldLake2 work again	Duncan Laurie
2012-11-12	ACPI: Zero pstate/cstate control values in FADT	Duncan Laurie
2012-11-06	Drop redundant CHIP_NAME in mainboard.c	Kyösti Mälkki
2012-10-08	hpet: common ACPI generation	Patrick Georgi
2012-10-05	Use mainboard_interrupt_handlers everywhere	Patrick Georgi
2012-08-08	Cleanup coreboot memory table includes	Kyösti Mälkki
2012-08-08	Drop HAVE_MAINBOARD_RESOURCES	Kyösti Mälkki
2012-08-01	Intel and GFXUMA: drop redundant use of lb_add_memory_range()	Kyösti Mälkki
2012-07-26	Drop mainboard chip.h	Stefan Reinauer
2012-07-24	ChromeOS: Remove board specific acpi_get_vdat_info()	Stefan Reinauer
2012-07-24	Drop (empty) sandybridge_late_initialization()	Stefan Reinauer
2012-07-24	Remove CMOS Extended range enable from romstage	Duncan Laurie
2012-07-24	Move GGL0001 ACPI code to generic ChromeOS code	Stefan Reinauer
2012-05-26	Move subsystem IDs to devicetree.cb	Stefan Reinauer
2012-05-03	Don't pre-enable SATA AHCI in romstage.c	Stefan Reinauer
2012-05-02	ChromeOS: drop unused debug header description	Stefan Reinauer
2012-05-01	Drop CONFIG_MAX_PHYSICAL_CPUS on non-AMD boards	Stefan Reinauer
2012-05-01	Clean up Emerald Lake 2 mainboard directory	Gabe Black
2012-05-01	Allow more CPU cores on Emerald Lake 2 CRB	Stefan Reinauer
2012-05-01	Set up ChromeOS dev mode, recovery, and write protect GPIOs on Emerald Lake 2.	Gabe Black
2012-05-01	Fix Sandybridge/Ivybridge mainboards according to code review	Stefan Reinauer
2012-05-01	Set up the Emerald Lake 2 SMI and SCI sources based on the schematic.	Gabe Black
2012-04-30	Add support for Intel Emerald Lake 2 CRB	Stefan Reinauer