coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-01-06	cpu/intel/model_206ax: Rename `cX_acpower` options	Angel Pons
2021-01-06	cpu/intel/model_206ax: Unify ACPI C-state options	Angel Pons
2020-03-29	drivers/intel/gma/acpi: Provide default definition for displays	Nico Huber
2020-01-10	mb/intel/emeraldlake2/devicetree.cb: Align contents	Angel Pons
2019-07-19	sb/intel/{bd82x6x\|ibexpeak}: Drop p_cnt_throttling_supported	Patrick Rudolph
2019-06-21	sb/intel/bd82x6x: Set up io_gen_dec in romstage based on devicetree	Arthur Heymans
2019-01-24	cpu/intel/model_206ax: Remove the notion of sockets	Arthur Heymans
2019-01-23	mb///devicetree.cb: Make sandybridge devicetree uniform	Arthur Heymans
2015-05-28	igd.asl rewrite	Vladimir Serbinenko
2014-11-23	sandy/ivy/nehalem: Remerge interrupt handling	Vladimir Serbinenko
2014-11-08	bd82x6x: Move to common FADT.	Vladimir Serbinenko
2014-01-12	ibexpeak / bd82x6x: Make SATA mode user-visible option.	Vladimir Serbinenko
2013-02-14	sconfig: rename lapic_cluster -> cpu_cluster	Stefan Reinauer
2013-02-14	sconfig: rename pci_domain -> domain	Stefan Reinauer
2012-05-01	Set up the Emerald Lake 2 SMI and SCI sources based on the schematic.	Gabe Black
2012-04-30	Add support for Intel Emerald Lake 2 CRB	Stefan Reinauer