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Update Kconfig to remove unrelated configs inheritted from JSL_RVP.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Ia744b57302f7c8310c42e12cf019b7f6e7b8f9e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48544
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update memory parameters based on memory type supported by
Elkhart Lake CRB:
1. Update spd data for EHL LPDDR4X memory
- DQ byte map
- DQS CPU-DRAM map
- Rcomp resistor
- Rcomp target
2. Add configurations for vref_ca & interleaved memory
3. Add EHL CRB on board LPDDR4X SPD data bin file
4. Update mainboard related FSPM UPDs as part of memory
initialization
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Ifd85caa9ac1c9baf443734eb17ad5683ee92ca3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Update Elkhartlake CRB devicetree devices based on EHL EDS.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I88097ced03f4376f309487b9d5207473f77742ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Remove JSL specific SMBIOS sku id info as it is not required by
EHL.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Ib672eb456ba62f2eb7f941630c4fbb34823664f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48123
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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THis patch removes IPU & MIPI related support from EHL CRB as they
are not supported in EHL.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I3eb038009daaabd048f40c7953cb2c111cd4fe63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Since there is no EC support on EHL CRB, this patch removes board
ID detection via EC (board_id.c & board_id.h) and its related
files. Temporarily removes variant_memcfg_config function in
romstage_fsp_param.c, will be added back when updating memory
configs later.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I40d96285dc05ec5faabc123950b6b3728299e99a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48121
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since EHL CRB does not support ChromeOS, this patch removes
ChromeOS EC related headers (ec.h & gpio.h) and #includes.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I9c0c3722065c041769081f3d564646ce6a565a9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Since there is no ChromeOS support for EHL CRB, drop smihandler.c
which just deals with ChromeOS support.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Id474c3b04a82c03dda6514cc4565b58fb790b9c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Since ChromeOS is not officially supported for EHL CRB, removing
ChromeOS related codes. Here are the change details:
- Remove ChromeOS related kconfig switches, including
SOC_INTEL_CSE_LITE_SKU which has dependency on ChromeOS flag
- Remove chromeos.c file
- Remove ChromeOS dsdt related codes from dsdt.asl & mainboard.c
- Remove ChromeOS GPIO related codes from variants.h & gpio.c
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I4aabd40a4b46d4e64534b99e84e0523eaeaff816
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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"Die()" needs <console/console.h>, as per this patch:
https://review.coreboot.org/c/coreboot/+/45540
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I0f9fae4a1e43477ca8e78ebbebd8c0729f8b7668
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48116
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is a initial mainboard code cloned entirely from jasperlake_rvp
aimed to serve as base for further mainboard check-ins.
This patch is based on TGL_upstream series patches:
https://review.coreboot.org/c/coreboot/+/37868
List of changes on top off initial jasperlake_rvp clone:
1. Replace "Jasperlake" with "Elkhartlake"
2. Replace "jsl" with "ehl"
3. Replace "jslrvp" with "ehlcrb"
4. Remove unwanted SPD file, add empty SPD as placeholder
6. Empty romstage_fsp_params.c, to fill it later with SOC specific
config
7. Empty GPIO configurations, to be filled as per board
8. Empty memory.c configurations, to be filled as per board
9. Add board support namely BOARD_INTEL_ELKHARTLAKE_CRB
10. Replace jslrvp variant with ehlcrb variant
Changes to follow on top of this:
1. Add correct memory parameters, add SPDs
2. Clean up devicetree as per tigerlake SOC
3. Add GPIO support
4. Update ehl fmd file to replace 32MB chromeos.fmd
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I2cbe9f12468318680b148739edec5222582e42a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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