Age | Commit message (Expand) | Author |
---|---|---|
2019-08-26 | soc/intel: Use common romstage code | Kyösti Mälkki |
2019-08-18 | cpu/intel: Enter romstage without BIST | Kyösti Mälkki |
2019-04-13 | sb/intel/i82801jx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB | Patrick Rudolph |
2019-03-04 | arch/io.h: Drop unnecessary include | Kyösti Mälkki |
2019-03-01 | device/pci: Fix PCI accessor headers | Kyösti Mälkki |
2019-01-10 | mb: Move timestamp_add_now to northbridge x4x | Elyes HAOUAS |
2019-01-09 | cpu/intel: Use the common code to initialize the romstage timestamps | Arthur Heymans |
2018-10-15 | sb/intel/i82801jx: Use macros for LPC_EN | Arthur Heymans |
2018-08-13 | mb/intel/dg43gt: Enable the GBE | Arthur Heymans |
2018-01-05 | nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeout | Arthur Heymans |
2017-09-23 | mb/intel/dg43gt: Add romstage timestamps | Arthur Heymans |
2017-08-10 | mb/intel/dg43gt: Add mainboard | Arthur Heymans |