coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2018-06-29	sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables	Arthur Heymans
	Both southbridges need to be done at once since this southbridge code is used for different northbridges, which fails to compile when done separately. This needs an acpi_name functions in the northbridge code to be defined. TESTED on Intel DG43GT: show correct PIRQ ACPI entries in /sys/firmware/acpi/tables/SSDT. Change-Id: I286d251ddf8fcae27dd07011a1cd62d8f4847683 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14	nb/intel/x4x: Deprecate native graphic init	Arthur Heymans
	Libgfxinit provides a better alternative to the native C init. While libgfxinit mandates an ada compiler, we want to encourage use of it since it is in much better shape and is actually maintained. This way libgfxinit also gets build-tested by Jenkins. Change-Id: I4843f52307b87cff6fa6f4d0c74b87428fefa8ac Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14	mb//: Enable libgfxinit on x4x boards	Arthur Heymans
	TESTED Intel DG41WV with VGA, Intel DG43GT with VGA and HDMI1 and HDMI2. Change-Id: I774b79cc0ef9dc72ccf48901ab94376b27ed9c7a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-12	drivers/intel/gma: Unify VBT related Kconfig names	Nico Huber
	Shuffle words and drop the _DATA_FILE suffix. Change-Id: I0b0d50ea729e5580c0bc7b43f250ff387ce59cfc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-06	mb//: Add a few VBT files	Arthur Heymans
	These files are directly extracted from the vendor firmware. Change-Id: I1dea2843255e4a3e93fbb734dea284be029dbc45 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-04	mb/intel: Get rid of whitespace before tab	Elyes HAOUAS
	Change-Id: I891b056b64fde27ef0e351f8cf24a258fb5cabfa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-26	mainboard/intel/dg41wv: Fix lint check error	Maulik V Vaghela
	Fix lint error due to non-ASCII characters BUG=none BRANCH=none TEST=check if no error in checkpatch.pl script. Change-Id: Iec7682e460c8e0d467a70349a23390554cc1de92 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26562 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-26	mb/intel/dg41wv: Add mainboard	Arthur Heymans
	This board was used a test target for the x4x DDR3 raminit patches and has an easy to access DIP8 socket. What is tested and works: * S3 resume * PEG, PCI, USB, SATA * Sound * Ethernet * Native graphic init (textmode and linear fb) on the VGA output * Passing memtest86+ with 2 2Rx8 4G dimms * PS2 Keyboard * Flashing coreboot internally from vendor BIOS. What does not work: * Running dram at 533 MHz (limited at 400MHz currently) Tested with two 4G dual rank DDR3 dimm, booted SeaBIOS and Linux 4.10. Change-Id: If01bf658e52d273c3c203d362f21c3cb9c623f40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20003 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>