coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-03-03	mb/{intel/d510mo,foxconn/d41s}/devicetree.cb: Remove PEG device	Arthur Heymans
2021-03-03	mb/intel/d510mo/devicetree.cb: Indent with tabs	Arthur Heymans
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-10	src/mainboard: Replace GPLv2 long form headers with SPDX header	Elyes HAOUAS
2020-03-18	mainboard/[g-p]*: Remove copyright notices	Patrick Georgi
2019-06-06	sb/intel/i82801gx: Detect if the southbridge supports AHCI	Arthur Heymans
2019-01-08	mb/{d41s,d510mo}: Remove references to PCIe port 5 and 6	Arthur Heymans
2018-11-12	mb//: Harmonise FD and devicetree on boards featuring ICH7	Arthur Heymans
2017-09-22	mb/intel/d510mo: Use common ramstage driver to configure the ck505	Arthur Heymans
2016-02-09	mb/intel/d510mo: Explicitly select NIC on PCI in devicetree	Damien Zammit
2016-01-28	mb/intel/d510mo: Use SATA AHCI by default	Damien Zammit
2016-01-28	mb/intel/d510mo: Use native gfx initialization	Damien Zammit
2016-01-28	mb/intel/d510mo: Add missing GPIO and GPEN	Damien Zammit
2015-12-02	mainboard/intel/d510mo: Add Intel D510MO mainboard	Damien Zammit