coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
	Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " \|egrep ":( /\.\/\$\|#\|;#\|-- \| \ )" \| cut -d: -f1 \|grep -v crossgcc \|grep -v gcov \| grep -v /elf.h \|grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. /") -# This file is part of a set of unofficial pre-commit hooks available -/ This file is part of coreboot / -# This file is part of msrtool. -/ This file is part of msrtool. / - This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. / - This file is part of the coreboot project. - /* This file is part of the coreboot project. / -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/ This file is part of the coreboot project / -/ This file is part of the coreboot project. / -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. / -/ This file is part of the ectool project. / - This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. / -## This file is part of the superiotool project. -/ This file is part of the superiotool project / -/ This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-10	src/mainboard: Replace GPLv2 long form headers with SPDX header	Elyes HAOUAS
	Change-Id: I64d9468682a4aae3084b17b8724d035f17d01dff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-18	mainboard/[g-p]*: Remove copyright notices	Patrick Georgi
	They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I426518e8e18de1c8efcfb7ecb0835df3e257dca1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39608 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06	sb/intel/i82801gx: Detect if the southbridge supports AHCI	Arthur Heymans
	This automatically detects whether the southbridge supports AHCI. If AHCI support is selected it will be used unless "sata_no_ahci" is set in the devicetree to override the behavior. Change-Id: I8d9f4e63ae8b2862c422938f3103c44e761bcda4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-08	mb/{d41s,d510mo}: Remove references to PCIe port 5 and 6	Arthur Heymans
	The southbridge has the function disable bits for port 5 and 6 strapped RO to 1 (disable). Change-Id: I2948935d42b9031d61f9e5b3f06b769e68f5a042 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-11-12	mb//: Harmonise FD and devicetree on boards featuring ICH7	Arthur Heymans
	On some boards the devicetree and Function Disable register did not match. In this case the FD values are put in the devicetree as these were the values that were actually used in practice. A complete devicetree will make it easier to automatically disable devices in ramstage. Change-Id: I1692ca5f490ea84e2fc520d3f66044ad7514f76e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-09-22	mb/intel/d510mo: Use common ramstage driver to configure the ck505	Arthur Heymans
	TESTED, the screen doesn't jiggle (caused by wrong clock on reset default clockgen configuration) Change-Id: Icfa22daf90f9e2eff13b4fc5994664e96903dd1e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09	mb/intel/d510mo: Explicitly select NIC on PCI in devicetree	Damien Zammit
	While the board configuration still works without this, It's nicer to have the device statically defined since the NIC is hardwired to the board. Change-Id: Ic6682865dd17672c3782bfba9511cd120d1657c1 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13455 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28	mb/intel/d510mo: Use SATA AHCI by default	Damien Zammit
	Change-Id: I6f9772c5bcf9a50dfbc3d1cfaeb79f4454d1fb27 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13454 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-01-28	mb/intel/d510mo: Use native gfx initialization	Damien Zammit
	Change-Id: Ic4de7a762e90b379be3814afc61467e1cd099215 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13034 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-28	mb/intel/d510mo: Add missing GPIO and GPEN	Damien Zammit
	Change-Id: I56c0a55d57d8beabcb33cf1984b037556a71a8b9 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13452 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-02	mainboard/intel/d510mo: Add Intel D510MO mainboard	Damien Zammit
	Board uses Pineview native raminit Board boots from grub to linux kernel VGA needs work, currently headless machine Change-Id: I8e459c6d40e0711fac8fb8cfbf31d9cb2aaab3aa Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/10074 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>