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It's commented in <types.h> that it shall provide <commonlib/helpers.h>.
Fix for ARRAY_SIZE() in bulk, followup works will reduce the number
of other includes these files have.
Change-Id: I2572aaa2cf4254f0dea6698cba627de12725200f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Rework Kconfig file that each variant has its own config option with
their specific selects / configuration and move common selects to
`BOARD_INTEL_COFFEELAKE_COMMON`, which is used as base for each
variant.
Also, move selects from Kconfig.name to Kconfig so that the
configuration is at one place and not distributed over two files.
Built each variant with `BUILD_TIMELESS=1` and all generated
coreboot.rom files remain identical. Excluded the .config file by
disabling `INCLUDE_CONFIG_FILE` to make this reproducible.
Change-Id: I3b3d3cff5ea7a3f4d1c4ddd911240763e4891e06
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
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FSP-S hides the PMC from the PCI bus when it runs, but there are still
initialization steps coreboot programs for the PMC. Therefore, change
all of the cannonlake mainboards to set the PMC as hidden in the
devicetree, which means the device will be skipped during enumeration,
but device callbacks are still issued as if the device were enabled.
TEST=Ran full patch train on google/dratini, disassembled SSDT and the
PEPD device matches what is in pep.asl. Also verified via dmesg that the
INT33A1 device is still initialized by the kernel.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib4a20ce9075ce7653388a5d3e281fe774bf89355
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Specify the type of the `DIMM_SPD_SIZE` Kconfig symbol once.
Change-Id: I619833dbce6d2dbe414ed9b37f43196b4b52730e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the
default by changing its enum value to 0 and remove its configuration
from all related devicetrees.
If `common_soc_config.chipset_lockdown` is not configured with
something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT`
is used.
Also, add a release note for the upcoming 4.15 release.
Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Specify the type of the `VARIANT_DIR` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: Iea2f992a59e41e00fec3cdc9d6a13b5f3ab0a437
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56558
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Specify the type of the `FMDFILE` Kconfig symbol once instead of doing
so on each and every mainboard.
Change-Id: I810bd3fe8d42102586db6c2c58b7037a60189257
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56557
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Specify the type of the `OVERRIDE_DEVICETREE` Kconfig symbol once
instead of doing so on each and every mainboard.
Change-Id: I4cbf4e318a30f0cf75aa8690e7454b9caa115c9d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56556
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Specify the type of the `DEVICETREE` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: If68f11a5ceaa67a3e8218f89e1138c247ebb9a25
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56555
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once
instead of doing so on each and every mainboard.
Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, internal flashing is not possible due to FSP lockdown. Thus
let coreboot do chipset lockdown on all variants.
Change-Id: Ib25a0543bfee0889dce071f3b01725daabd0a0eb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56407
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Even the boards with MAINBOARD_HAS_CHROMEOS need to be build-tested
with CHROMEOS=n.
Change-Id: I16fcf62a23dae1b21c77cee275c867f9c1de893b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Change-Id: I4356a8bda71e84afe8c348d366479c5006bf2459
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49796
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Objects that are created with acpigen need to be declared
with External () for the generation of dsdt.asl to pass
iasl without errors.
There are some objects that are common to all platforms,
and some that should be declared only conditionally.
Having a top-level ASL helps to achieve this.
Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.
Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).
Change-Id: Ib827e9b2919dbd0e16f30b8dfde46348365d9622
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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One of the variants lacks an hda_verb.h, and hda_verb.c can't be built.
Follow-up changes will make mainboard hda_verb.c files always get built
through AZALIA_PLUGIN_SUPPORT, and breaks building this contraption.
Turn the headers into standalone compilation units to prevent this
issue. Since they contain definitions, including them from multiple
compilation units wasn't a good idea anyway.
Change-Id: I00d968563539a4e1b8d1e12145293439d8358555
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48360
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove SOC_INTEL_COMMON_BLOCK_HDA from mainboards Kconfig since it is
selected by their SoC soc/intel/cannonlake.
Change-Id: I9597746a217575b42f6325998b948e16b452231a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48289
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change reorganizes the CNVi device entries in mainboard
devicetree/overridetree and SoC chipset tree to make it consistent
with how other SoC internal PCI devices are represented i.e. without a
chip driver around the SoC controller itself.
Before:
chip drivers/wifi/generic
register "wake" = "..."
device pci xx.y on end
end
After:
device pci xx.y on
chip drivers/wifi/generic
register "wake" = "..."
device generic 0 on end
end
end
Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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The dt option `speed_shift_enable` is obsolete now. Drop it.
Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This change switches all mainboard devices to use drivers/wifi/generic
instead of drivers/intel/wifi chip driver for Intel WiFi
devices. There is no need for two separate chip drivers in coreboot to
handle Intel and non-Intel WiFi devices since the differences can be
handled at runtime using the PCI vendor ID. This also allows mainboard
to easily multi-source WiFi chips and still use the same firmware
image without having to distinguish between the chip drivers.
BUG=b:169802515
BRANCH=zork
Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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This patch moves platform.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.
TEST=Able to build and boot TGL, CNL and CML platform.
1) Dump and disassemble DSDT, verify _PIC method present inside
common platform.asl is still there.
2) Verify no ACPI error seen while running 'dmesg` from console.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I5189b03d6abfaec39882d28b40a9bfa002128be3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Drop GENERIC_SPD_BIN from boards selecting it, despite having no
soldered memory.
Change-Id: Id05fe45007d5662ff9bee326f28470df1206fcff
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45146
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I3fdc521d30155c4275c336afe03244311f584e71
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44617
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Setting USBx_PORT_EMPTY is not a requirement anymore, since unset
devicetree settings default to 0 and the OC pin now only gets set when
the USB port is enabled (see CB:45112).
Thus, drop the setting from all devicetrees.
Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Since there are 4 different versions of FSPs for the Comet Lake
platform, add a new Kconfig option for the currently used SoC being able
to differ between the various SoCs and FSPs.
The new Kconfig option selects the Comet Lake SoC as base for taking
over its specific configuration and is only used for configuring the
path to its specific FSP header files and FSP binary.
Also, adjust all related mainboards so that their Kconfig selects the
new option.
For details, please see
https://github.com/intel/FSP/tree/master/CometLakeFspBinPkg
Built System76/lemp9 with BUILD_TIMELESS=1 before and after this patch
and both images are equal.
Change-Id: I44b717bb942fbcd359c7a06ef1a0ef4306697f64
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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Allow configuring FSP option PcieRpSlotImplemented. Also, update all
related devicetrees and configure PcieRpSlotImplemented to keep the
current behaviour.
Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Currently HECI1 gets enabled by the option HeciEnabled, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement/disablement of the HECI1 device.
All corresponding mainboards were checked if the devicetree matches
the HeciEnabled setting, and adjusted where necessary.
Change-Id: I03dd3577fbe3f68b0abc2d196d016a4d26d88ce5
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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Use tabs instead of eight (sometimes less) spaces.
Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Found using:
diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX' -- src/) |grep -v vendorcode |grep '<'
Change-Id: I5e14bf4887c7d2644a64f4d58c6d8763eb74d2ed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41827
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I3fad7cb2ac0b88adbe75acfa7a17f5a9b0bde6c2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41705
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Kconfig 4.17 started using the $(..) syntax for environment variable
expansion while we want to keep expansion to the build system.
Older Kconfig versions (like ours) simply drop the escapes, not
changing the behavior.
While we could let Kconfig expand some of the variables, that only
splits the handling in two places, making debugging harder and
potentially messing with reproducible builds (e.g. when paths end up
in configs), so escape them all.
Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
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Board devicetrees requests for drivers/pc80/tpm but that
was not included for the build. Note that there is actually
no on-board TPM, just an LPC header connector on these boards.
Change-Id: Ia959ae9072e3fc709b779b1fc778eb82e10c2ee3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Used commands:
perl -i -p0e 's|\/\*[\s*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-only */|' $(cat filelist)
perl -i -p0e 's|\/\*[\s*]*.*is[\s*]*free[\s*]*software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*either[\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License,[\s*]*or[\s*]*.at[\s*]*your[\s*]*option.[\s*]*any[\s*]*later[\s*]*version.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-or-later */|' $(cat filelist)
perl -i -p0e 's|\/\*[\s*]*.*is[\s*#]*free[\s*#]*software[;:,][\s*#]*you[\s*#]*can[\s*#]*redistribute[\s*#]*it[\s*#]*and/or[\s*#]*modify[\s*#]*it[\s*#]*under[\s*#]*the[\s*#]*terms[\s*#]*of[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*as[\s*#]*published[\s*#]*by[\s*#]*the[\s*#]*Free[\s*#]*Software[\s*#]*Foundation[;:,][\s*#]*either[\s*#]*version[\s*#]*3[\s*#]*of[\s*#]*the[\s*#]*License[;:,][\s*#]*or[\s*#]*.at[\s*#]*your[\s*#]*option.[\s*#]*any[\s*#]*later[\s*#]*version.[\s*#]*This[\s*#]*program[\s*#]*is[\s*#]*distributed[\s*#]*in[\s*#]*the[\s*#]*hope[\s*#]*that[\s*#]*it[\s*#]*will[\s*#]*be[\s*#]*useful[;:,][\s*#]*but[\s*#]*WITHOUT[\s*#]*ANY[\s*#]*WARRANTY[;:,][\s*#]*without[\s*#]*even[\s*#]*the[\s*#]*implied[\s*#]*warranty[\s*#]*of[\s*#]*MERCHANTABILITY[\s*#]*or[\s*#]*FITNESS[\s*#]*FOR[\s*#]*A[\s*#]*PARTICULAR[\s*#]*PURPOSE.[\s*#]*See[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*for[\s*#]*more[\s*#]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-3.0-or-later */|' $(cat filelist)
perl -i -p0e 's|(\#\#*)[\w]*.*is free software[:;][\#\s]*you[\#\s]*can[\#\s]*redistribute[\#\s]*it[\#\s]*and\/or[\#\s]*modify[\#\s]*it[\s\#]*under[\s \#]*the[\s\#]*terms[\s\#]*of[\s\#]*the[\s\#]*GNU[\s\#]*General[\s\#]*Public[\s\#]*License[\s\#]*as[\s\#]*published[\s\#]*by[\s\#]*the[\s\#]*Free[\s\#]*Software[\s\#]*Foundation[;,][\s\#]*version[\s\#]*2[\s\#]*of[\s\#]*the[\s\#]*License.*[\s\#]*This[\s\#]*program[\s\#]*is[\s\#]*distributed[\s\#]*in[\s\#]*the[\s\#]*hope[\s\#]*that[\s\#]*it[\s\#]*will[\#\s]*be[\#\s]*useful,[\#\s]*but[\#\s]*WITHOUT[\#\s]*ANY[\#\s]*WARRANTY;[\#\s]*without[\#\s]*even[\#\s]*the[\#\s]*implied[\#\s]*warranty[\#\s]*of[\#\s]*MERCHANTABILITY[\#\s]*or[\#\s]*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.[\#\s]*See[\#\s]*the[\#\s]*GNU[\#\s]*General[\#\s]*Public[\#\s]*License[\#\s]*for[\#\s]*more[\#\s]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist)
perl -i -p0e 's|(\#\#*)[\w*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist)
Change-Id: Ia01908544f4b92a2e06ea621eca548e582728280
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41178
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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.write_acpi_tables() should not be updating the device structure. This
change makes the struct device * argument to it as const.
Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I1ea2eebfdd43610e42b4cf04409ec76c2e8b0042
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These two identifiers were always very confusing. We're not filling and
injecting generators. We are filling SSDTs and injecting into the DSDT.
So drop the `_generator` suffix. Hopefully, this also makes ACPI look a
little less scary.
Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: David Guckian
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I426518e8e18de1c8efcfb7ecb0835df3e257dca1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39608
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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wpsw_boot is deprecated in favour of wpsw_cur. As such,
coreboot no longer needs to share "write protect" GPIO
with depthcharge.
BUG=b:124141368, chromium:950273
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I2fcb7f82aa063fd72928171af5cbef0356ba620c
Signed-off-by: Joel Kitching <kitching@google.com>
Cq-Depend: chromium:2088434
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39318
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Due to build rules, dummy acpi_tables source files were added in many
mainboards. With commit 1e83e5c61a3aa98f58f7d8cbf8d1eb9532896cc3
("src/arch/x86: Build mainboard acpi_tables source if present"),
the build system will build mainboard acpi_tables only if present. Remove
the dummy/empty/blank acpi_tables source files.
BUG=None
TEST=Build test with some google mainboards.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0cef34368e2e5f5e3b946b22658ca10c7caad90a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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This patch creates a common instance of northbridge.asl inside intel common
code (soc/intel/common/block/acpi/acpi) and changes cnl,icl & tgl soc code to
refer northbridge.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
Device(MCHC) presence after booting to OS.
Change-Id: Ib9af844bcbbcce3f4b0ac7aada43d43e4171e08b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38155
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Previously, each Intel chipset had its own sleepstates.asl file.
However, this is no longer the case, so drop these comments.
Change-Id: I50aba6e74f41e2fa498375b5eb6b7e993d06bcac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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It provides no useful information, so it might as well vanish.
Change-Id: I0df6f4639a16058486c2e2d40fe4067d65670731
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This patch moves the common devicetree settings into baseboard and
creates overridetree.cb for each variant. For PCIe root port settings,
SATA, eMMC, I2Cs and GBe, they are in overridetree.
TEST=build an image for each variant
Change-Id: I067bdb3fcf1218b93e52801f6db093e24d7d2b62
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36794
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch renames COMETLAKE_RVP to COMETLAKE_RVPU to avoid confusion.
TEST=build an image with COMETLAKE_RVPU
Change-Id: I93d7b5cc0be475926bb92503b66797dc67e607f5
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36793
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ic92e08ae5b741889a8200d10ea8148e4b4384dc8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37270
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Guckian
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch creates a common instance of globalnvs.asl/nvs.h inside intel common
code (soc/intel/common/block/) and ask cnl & icl soc code to refer globalnvs.asl
and nvs.h from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
GNVS operation region presence after booting to OS.
Change-Id: Ia9fb12a75557bd7dc38f6d22ba2b32065d18b3ee
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch creates a common instance of sleepstates.asl inside intel common
code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to
refer sleepstates.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
S0/S3/S4/S5 entries after booting to OS.
Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use explicit simple PCI config accessors here.
Change-Id: Ifa3814fdd7795479ca5fdbfc4deb3fe8db9805f3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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Increases CPU max core count to 16 for coffeelake Refresh-S Platform.
TEST: boot to linux OS on CFL-S refresh Intel RVP and verified the output
of cat /proc/cpuinfo shows no of processor=16.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I579ff6ae8227844741406c503d3994408ec2b617
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34156
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch configures FSP UPD values for HPD and DDC of DDI ports for
WHLRVP.
BUG=none
TEST=Tested that eDP & DP works on WHLRVP
Signed-off-by: Usha P <usha.p@intel.com>
Signed-off-by: sridhar <sridhar.siricilla@intel.com>
Change-Id: I576469f5564e3e56159762752dbe4557e9dc1912
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33435
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Also clean up cannonlake_memcfg_init.
The major changes include:
(1) Add enum 'mem_info_read_type' to spd_info.
(2) Add per-dimm-slot spd_info to cnl_mb_cfg.
(3) Setup memory config for each slot independently.
(4) Squash meminit_memcfg_spd().
BUG=chromium:960581, b:124990009
BRANCH=none
TEST=boot hatch, hatch_whl, and kohaku
Change-Id: I686a85996858204c20fd05ef24787a0487817c34
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32513
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The gpio table is only used by depthcharge, and depthcharge rarely
has a need for the "recovery" gpio. On a few boards it does use the
gpio as a signal for confirming physical presence, so on that boards
we'll advertise the board as "presence".
All these strings probably should have been #defines to help avoid
typos (e.g., the "ec_in_rw" in stout seems questionable since everybody
else uses "EC in RW").
Cq-Depend: chromium:1580454
BUG=b:129471321
BRANCH=None
TEST=Local compile and flash (with corresponding changes to depthcharge)
to 2 systems, one with a "presence" gpio and another without. Confirmed
that both systems could enter dev mode.
Change-Id: Id6d62d9e48d3e6646cbc1277ea53f0ca95dd849e
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Another run of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I3243197ab852a3fbc3eb2e2e782966a350b78af2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This patch configures FSP UPD values for HPD and DDC of DDI ports for
CMLRVP.
BUG=none
TEST= Tested that eDP works on CMLRVP.
Change-Id: If8c8480eaf2d63cec0b5598b5af3088c630dd78a
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32140
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I0e1a66b3d1d7bd4633ad1df597f62ddbd38f46d4
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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This patch overrides required LPSS FSP UPDs for CMLRVP from devicetree.cb
File devicetree-override.cb will override required UPDs and is only
applicable to CML soc for now
Change-Id: I82e3323df952762e2d9c14f1e3cfa75872ccc9b4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31285
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds support to select CMLRVP board.
Change-Id: I5f81b47f33345edefa0a7064559d9531e1d20eff
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Clone entirely from mainboard/intel/coffeelake_rvp/../whl_u
commit id: 73916defba8d036c2536e1b37a1449ac16e5f56f
Change-Id: Icc32a6e1940ba2d13f3ad74cddbb4b75a637cc18
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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For Chrome OS (or vboot), The PRESERVE flags should be applied on
following sections:
RO_PRESERVE, RO_VPD, RW_PRESERVE, RW_ELOG, RW_NVRAM, RW_SMMSTORE,
RW_VPD, RO_FSG (b:116326638), SI_GBE (chromium:936768),
SI_PDR (chromium:936768)
With the new PRESERVE flag, we don't need RO_PRESERVE and RW_PRESERVE in
the future. But it's still no harm to use it if there are multiple
sections all needing to be preserved.
BUG=chromium:936768
TEST=Builds google/eve and google/kukui inside Chrome OS source tree.
Also boots successfully on eve and kukui devices.
Change-Id: I6664ae3d955001ed14374e2788d400ba5fb9b7f8
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This patch performs below tasks
1. Create SOC_INTEL_COMMON_CANNONLAKE_BASE kconfig.
2. Allow required SoC to select this kconfig to extend CANNONLAKE
SoC support and add incremental changes.
3. Select correct SoC support for hatch, sarien, cflrvps
and whlrvp.
* Hatch is WHL SoC based board
* Sarien is WHL SoC based board
* CFLRVP U/8/11 are CFL SoC based board
* WHLRVP is based on WHL SoC
4. Add correct FSP blobs path for WHL SoC based designs.
Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch ensures to select chromeos kconfig only for required
CFL-U and WHL-U RVPs supported by Intel client team.
TEST=Ensure CONFIG_GBB_FLAG_FORCE_MANUAL_RECOVERY is only selected
for CFL-U and WHL-U boards.
Change-Id: Ib61409402a948f8d5f91130e200c45320ea13d3d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31214
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes duplicate selects of same SOC_INTEL_CANNONLAKE_MEMCFG_INIT
from various CFL/WHL SoC based boards to include cnl_memcfg_init.c file
and include the cnl_memcfg_init.c file by default in CNL SoC Makefile.inc.
Change-Id: Ib21ea305871dc859e7db0720c18a9479100346c3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch ensures to enable IFD GBE region only for required
CFL RVP8 and 11 supported by Intel IOTG team.
TEST=Ensure CONFIG_MAINBOARD_USES_IFD_GBE_REGION is not selected
for CFL-U and WHL-U boards
Change-Id: If3fcd23c32f9afd2004fb176c0324f089f2ee412
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Remove hard coding for SaGv config in devicetree.cb and apply macro for
SaGv config for CNL variants boards
Change-Id: If007589d5c1368602928b1550ec8788e65f70c05
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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need it
Hide "Add gigabit ethernet firmware" option for boards that do not
use GbE firmware in GbE section.
The option is now hidden by default and can be reenabled on a
per-board basis by selecting MAINBOARD_USES_IFD_GBE_REGION in the
mainboards Kconfig.
The following boards seem to use this:
mb/roda/rv11
mb/ocp/wedge100s
mb/ocp/monolake
mb/lenovo/x230
mb/lenovo/x220
mb/lenovo/x201
mb/lenovo/x200
mb/lenovo/t530
mb/lenovo/t520
mb/lenovo/t430s
mb/lenovo/t430
mb/lenovo/t420s
mb/lenovo/t420
mb/lenovo/t400
mb/kontron/ktqm77
mb/intel/saddlebrook
mb/intel/kblrvp
mb/intel/dg43gt
mb/intel/dcp847ske
mb/intel/coffeelake_rvp
mb/intel/camelbackmountain_fsp
mb/hp/revolve_810_g1
mb/hp/folio_9470m
mb/hp/compaq_8200_elite_sff
mb/hp/8770w
mb/hp/8470p
mb/hp/8460p
mb/hp/2760p
mb/hp/2570p
mb/google/sarien
mb/facebook/watson
mb/compulab/intense_pc
mb/asus/maximus_iv_gene-z
The boards were identified by looking at devicetree.cb, but this
list is possibly still incomplete.
Change-Id: Ibfb07902ad93fe5ff2bd4f869abcf6579f7b5a79
Signed-off-by: Jan Tatje <jan@jnt.io>
Reviewed-on: https://review.coreboot.org/c/30790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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After a96e66a (soc/intel: Clean mess around UART_DEBUG) got merged,
all mainboard using intel cannonlake,coffeelake, kabylake, skylake,
icelake and whiskeylake get affected.
Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG
and set default console for each platform.
TEST=Intel client and IoT team has verified that LPSS uart
is working fine on CNL, WHL and ICL RVPs.
Change-Id: I0381a6616f03c74c98f837e3c008459fefd4818c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30913
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Does not fix 3rdparty/, *.S or *.ld or yet.
Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/17656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Update mainboard UART Kconfig for Whiskylake RVP.
TEST=Build and test on Whiskylake RVP.
By default we can still get console from cbmem, and
enable CONSOLE_SERIAL can get logs from UART port2.
Select other Coffeelake RVPs and check CONSOLE_SERIAL is enabled.
Change-Id: Ic56c019a12b467e5bede5648098d3fb82b56ba7e
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-on: https://review.coreboot.org/c/30861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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Most boards currently do not use EC firmware from SPI flash in the
IFD, this hides this option by default and shows it only for boards
that need it.
A new config variable MAINBOARD_USES_IFD_EC_REGION is introduced to
enable this option for boards that need it.
The following list of boards requiring this was provided by
Lijian Zhao:
1. intel/cannonlake_rvp
2. intel/coffeelake_rvp
3. intel/icelake_rvp
4. google/sarien
5. google/hatch
Change-Id: I52ab977319d99a23a5e982cc01479fe801e172a7
Signed-off-by: Jan Tatje <jan@jnt.io>
Reviewed-on: https://review.coreboot.org/c/30697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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Report correct board information for Whiskeylake RVP to OS.
Use short board name like other RVP as it's used
for firmware version check in auto test.
Change-Id: I3f7c95f136e39b978a335cc7855cac819043db7c
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-on: https://review.coreboot.org/c/30318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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Field 'OEMID' & "OEM Table ID" are related to DSDT table
not to mainboard.
So use macro to set them respectvely to "COREv4" and
"COREBOOT".
Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
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DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version.
This will cause the AML interpreter to use 32-bit integers and math
if the version is 1, and 64-bit if the version is >=2.
Current spec version is 2 for ACPI 6.2-a.
Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29626
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable HDA controller coreboot driver for Whiskey Lake RVP platform on
top of common code.
BUG=N/A
TEST=Build and boot up on whiskey lake rvp board, comfirm audio playback
is working.
Change-Id: I7daf1c741b92ff59b9cb4030d218e9c1054c4b79
Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com>
Reviewed-on: https://review.coreboot.org/28781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
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Remove the SmbusEnable parameter from all Cannon Lake mainboards.
Instead this will be determined by the enable state of the SMBUS
PCI device.
Change-Id: I7ece6768da4c517747af12a07012583575816ae1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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generation
This changes uses drivers/intel/wifi chip for CNVi device to ensure that:
1. Correct device name shows in ACPI name space
2. Correct wake up shows in cat /proc/acpi/wakeup
3. Remove cnvi.asl from soc/intel/cannonlake
Change-Id: Ic81de2dce6045ced913766790a40ed19119f5118
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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this patch adds following changes
- Select config to initialize codecs in common HDA driver.
- Add audio verb table for coffee lake RVP11 & RVP8.
BUG: None
TEST: boot to yocto linux and windows os on CFL RVP11 & RVP8. verified audio
playback and record functionality over anolog audio jack & HDMI display.
Change-Id: I567e317c0e9ac9f91e159866c7f896e4c101712b
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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- Add new mainboard variant coffee lake RVP8, which is CRB for
coffee lake-s processor, support U-DIMM DDR4 memory module.
- Modify cfl_h devicetree to enable IO devices, configure PCIE root
port clock source, usb over current pin as per board schematics.
- Select cannonlake PCH-H chipset config for both cfl_h & cfl_s.
- Add GPIO table as per board schematics.
BUG= None
TEST= Build and flash, confirm boot into yocoto & windows OS on both
cfl RVP11 & RVP8 platform. verified PCI, USB, ethernet, SATA,
display, power functionalities.
Change-Id: Iabd32eb43ee8e6b1a3993ba4e083a80c62485b14
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29066
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Enable Gigabit Ethernet network controller on whiskey lake rvp platform,
add NVM bin file as well.
BUG=N/A
TEST=Build and boot up into chromeos on whiskey lake rvp platform, and
check eth0 can get IP address assigned,
Change-Id: Ia299a2aa78108175074e084cc34a7d2b38cf1c72
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27848
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some of the FSP silicon UPD entry can be updated base on device switch
in pci device tree, have both static config setting and device tree "on"
and "off" will be redundant.
BUG=N/A
TEST=Build and boot up fine with Whiskey Lake RVP platform.
Change-Id: Ia36cfab03c4613786e5580a039d89007b630adf9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27766
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new mainboard variant of whiskey lake rvp, which is primary
validation platform for whiskey lake silicon, support socket DDR4 memory
module.
BUG=N/A
TEST=Build and flash, confirm boot up into kernel on whiskey lake rvp
platform.
Change-Id: I4a5e8a9ec76d5e55e55ef9bf968825c17fbe9816
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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There's only DDR4 or LPDDR3 support for coffelake processor line,
details can be found out on EDS #570805.
BUG=N/A
TEST=N/A
Change-Id: I8ba6b6861b15b40b01237f87c8d55394f7fd6706
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Add gpio programming difference for whiskeylake rvp platform.
BUG=N/A
TEST=N/A
Change-Id: I35a0384f828fd3219e0c3adb4830f5bdab800e32
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28367
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Turn on SOC_INTEL_CANNONLAKE_MEMCFG_INT for coffeelake rvp platform
for easier collabration on newer platform. The setting in memory.c get
from board design itself.
BUG=N/A
TEST=Build and boot up with whiskey lake rvp platform.
Change-Id: I10f3af4bed511153cef4d6f3a93caea57cc4ae90
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28257
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Only for those that are x86 and also have a RW_LEGACY region.
The assumption is that all devices touched have 64k block sizes when
choosing size and alignment of the region.
Change-Id: I12addb137604f003d1296f34f555dae219330b18
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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TEST: same sha256sum with BUILD_TIMELESS=1.
Change-Id: Icf3368bcf1351f0e7cd4041c3792d76362aec9e5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
|
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Update SPD details to match with Coffeelake U RVP board
BUG=none
BRANCH=none
TEST=Boot on coffelake U rvp board and check if memory training is
passing and board boots till payload.
Change-Id: I953354cf5c6045731262f4f4e9da230187c2d246
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
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Update GPIO table as per board schematics.
GPIO table for other variants will be added later.
Change-Id: Ieb55d160ae2d6bff940840b1fba9411979332d4d
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
|
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Coffeelake U has 32MB flash chip support. Adding fmd file and enabling
CFL U board's Kconfig to output 32MB rom file.
Change-Id: I21431b7ac813781b12b95f80c6f8960a78caf4bc
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
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Add support for new board coffeelake RVP.
This patch is a copy patch and copies entire coffeelake_rvp folder from
cannonlake_rvp.
Changes done on top of copy:
1. Change copyright year from 2017 to 2018
2. Rename Cannonlake to Coffelake whenever applicable
3. Update entries in Kconfig and Kconfig.name
4. Rename variant directories to match coffeelake boards
Change-Id: Id37bfeb0ae51fd630fec96273216dbb2900782c7
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27904
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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