coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-08-07	soc/intel/cnl: Set Heci1Disable depending on devicetree config	Felix Singer
2020-07-14	src: Remove unused 'include <stdint.h>	Elyes HAOUAS
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-06	mainboard/intel: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	mainboard/[g-p]*: Remove copyright notices	Patrick Georgi
2019-12-05	mb/intel/coffeelake_rvp: Switch to overridetree setup	Gaggery Tsai
2019-12-02	src/mb/intel/coffeelake_rvp: Rename COMETLAKE_RVP to COMETLAKE_RVPU	Gaggery Tsai
2019-04-08	Replace remaining IS_ENABLED(CONFIG_*) with CONFIG()	Nico Huber
2019-03-18	mb/intel/coffeelake_rvp: Add cml_u board support	Subrata Banik
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2018-10-17	mb/intel/coffeelake_rvp: Add support for new coffee lake RVP8	praveen hodagatta pranesh
2018-10-08	Move compiler.h to commonlib	Nico Huber
2018-09-21	mb/intel/coffeelake_rvp: Add whiskey lake rvp	Lijian Zhao
2018-09-21	mb/intel/coffeelake_rvp: GPIO support for whiskey board	Lijian Zhao
2018-09-16	mb/intel/coffelake_rvp: Implement mainboard memory information	Lijian Zhao
2018-08-17	mb/intel/coffeelake_rvp: Update GPIO table for Coffeelake U RVP	Maulik V Vaghela
2018-08-14	mb/intel/coffeelake_rvp: Add support for new board coffeelake RVP	Maulik V Vaghela