coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2020-05-02	acpi: Move ACPI table support out of arch/x86 (3/5)	Furquan Shaikh
	This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" \| xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-01	mb/intel/cedarisland_crb: Enable P2SB device	Andrey Petrov
	Enable P2SB in static device tree so that hide/unhide trick works. Change-Id: I7dc20b001605b715155d333a07580e21a5f24136 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01	mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M	Andrey Petrov
	These parameters were found to work fine for 2-socket configuration, for FSP based on tag 16.D.21. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I466a7f2951ef307036ddaed0be0aacf98dd2710f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-30	mb/cedarisland_crb: rework GPIOs configuration using macros	Maxim Polyakov
	This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. The gpio.h file with PAD_CFG macros was automatically generated using the util/intelp2m [1] utility: ./intelp2m -p lbg -file cedarisland/vendorbios/inteltool_gpio.log According to the documentation [2], the Host Software Pad Ownership register only affects the pads that are configured as input. The intelp2m utility takes this into account when converting macros and ignores bits from this register for the corresponding pads. [1] https://review.coreboot.org/c/coreboot/+/35643 [2] Intel Document Number: 549921 Change-Id: Id671a9021a8313d8c3359b89c2934b929bcab1a4 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40736 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-30	mb/cedarisland_crb: exclude GPIOs reconfiguration by FSP-M	Maxim Polyakov
	We should be sure that after romstage the pads will be configured according to the config from gpio.h only. This patch sets the GPIO configuration from gpio.h using the soc/intel/common/gpio.c driver again in ramstage. [1] https://review.coreboot.org/c/coreboot/+/40730 Change-Id: Ic49e504d96fe4fd44434e7b981f8d8d9e76880ef Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-04-30	mb/intel/cedarisland_crb: use common driver to configure GPIO	Maxim Polyakov
	According to changes in the soc/xeon_sp code [1,2], server motherboards with Lewisburg PCH can use the soc/intel/common/gpio driver to configure GPIO controller. This patch adds pads configuration map, which has the format required by the GPIO driver. The data for this was taken from the inteltool register dump with vendors firmware. The gpio.h file with pad configuration was generated automatically using the util/intelp2m [3]: ./intelp2m -raw -p lbg -file cedarisland/vendorbios/inteltool_gpio.log [1] https: //review.coreboot.org/c/coreboot/+/39425 [2] https: //review.coreboot.org/c/coreboot/+/39428 [3] https: //review.coreboot.org/c/coreboot/+/35643 Change-Id: I90b91e6dbf8c65c747d0e0d94c61023e610f93ab Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-04-24	mb/intel/cedarisland_crb: Add dummy mainboard_memory_init_params()	Andrey Petrov
	Add a dummy implementation (currently FSP defaults are meant for CRB). It is needed only to prevent build breakage. Change-Id: I67b1a693886a29bdaf23f1f3f249da52ba65451a Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-03-26	mb/intel/cedarisland_crb: Add Cedar Island CRB	Andrey Petrov
	Just a minimal set of board files needed to get it to boot in 1 CPU mode. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: Ie2f944964e938d8026a6d5d8a22a8449199d08aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/39714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>