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2017-09-13mainboard/intel/cannonlake_rvp: Add dummy DSDT tableLijian Zhao
Add dummy ACPI DSDT table for cannonlake rvp platform. Change-Id: If45c2a7da7f5b20ddd3d56bf9d7f68a85d2f791d Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-11mainboard/intel/cannonlake_rvp: enable eMMCBora Guvendik
Set SCS emmc enable FSP parameter. Change-Id: Ib3d7a305c3bede439249204cf14d50e3eb8b6915 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21409 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-09-06Revert "soc/intel/cannonlake: Add dummy ACPI DSDT table"Kyösti Mälkki
This reverts commit 6c0f3c7ee1d53872851dbab636787852e3572c98. Reason for revert: Broke master builds, this was submitted out-of-order, some of the dependencies have not passed review with +2 yet. Change-Id: Ib7bcb1b98623d16e074caeca839a936d71ded709 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2017-09-06soc/intel/cannonlake: Add dummy ACPI DSDT tableLijian Zhao
A dummy DSDT table will be created for cannonlake. Change-Id: Ia435f2a03982313c6b0c63ac25668a3300d08793 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25mainboard/intel/cannonlake_rvp: SMBus, SAGV and Skip FSP MPInit in devicetreePratik Prajapati
Set SMBus, SAGV and Skip FSP MPInit configuration from devicetree.cb Change-Id: Ic810b003bf7fb13447d5d5dcd49cfcc31785b440 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-24mainboard/intel/cannonlake_rvp: set Max CPUs and Mainboard FamilyPratik Prajapati
Set MAX_CPUS and MAINBOARD_FAMILY for cannonlake RVP. Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: Ic6ef7e4f247ac2d227bab3b53512c659c5e72da7 Reviewed-on: https://review.coreboot.org/21152 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-23src/mainboard/intel/cannonlake: Add gpio support for cannonlakezhaojohn
Add gpio pins configuration for cannonlake rvp u/y boards. Change-Id: Ia077a070979401fe7bd23bda110d2b66a038d9fc Signed-off-by: john zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-22mainboard/intel/cannonlake_rvp: remove redundant devicetree.cbPratik Prajapati
devicetree.cb of cannonlake-u and y variant gets picked up from src/mainboard/intel/cannonlake_rvp/variants/cnl_[u/y] Change-Id: I83f636c93407a6fe17114582506397c46d1b4e20 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-22mainboard/intel/cannonlake-y: populate PCI devicesPratik Prajapati
Define and populate PCI devices in devicetree for CNL-Y RVP Change-Id: I311437798274dd48b0898f0832bf03d86fd9d3a6 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-08-22mainboard/intel/cannonlake-u: populate PCI devicesPratik Prajapati
Define and populate PCI devices in devicetree for CNL-U RVP Change-Id: Id04f5efe77a04c180b5dd392da777195bd9fb7a3 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-07-26intel/cannonlake_rvp: Split RVP boards and SPDLijian Zhao
Add both Cannonlake U DDR4 RVP and Cannonlake Y LPDDR4 RVP support. Implement SPD entry to FSPM for both platforms, seperated platform specific DQ/DQS/Rcomp input to FSPM as well. Change-Id: If71662353ddba89a9e831503a2d80dd5ebd65de3 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-19mainboard/intel/cannonlake_rvp: Add initial board filesAndrey Petrov
Initial board files needed to selected to build cannonlake rvp. Change-Id: I82bd5c785e451f02b827765c54d432517afd7de0 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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