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This change reorganizes the CNVi device entries in mainboard
devicetree/overridetree and SoC chipset tree to make it consistent
with how other SoC internal PCI devices are represented i.e. without a
chip driver around the SoC controller itself.
Before:
chip drivers/wifi/generic
register "wake" = "..."
device pci xx.y on end
end
After:
device pci xx.y on
chip drivers/wifi/generic
register "wake" = "..."
device generic 0 on end
end
end
Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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The dt option `speed_shift_enable` is obsolete now. Drop it.
Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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This change switches all mainboard devices to use drivers/wifi/generic
instead of drivers/intel/wifi chip driver for Intel WiFi
devices. There is no need for two separate chip drivers in coreboot to
handle Intel and non-Intel WiFi devices since the differences can be
handled at runtime using the PCI vendor ID. This also allows mainboard
to easily multi-source WiFi chips and still use the same firmware
image without having to distinguish between the chip drivers.
BUG=b:169802515
BRANCH=zork
Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Allow configuring FSP option PcieRpSlotImplemented. Also, update all
related devicetrees and configure PcieRpSlotImplemented to keep the
current behaviour.
Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I1ea2eebfdd43610e42b4cf04409ec76c2e8b0042
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I426518e8e18de1c8efcfb7ecb0835df3e257dca1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39608
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables SaGv on Intel CNL-Y and CNL-U RVP board
Change-Id: I8a4b8a2a365caed304935bf0d66db9a92d10c23f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31132
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove hard coding for SaGv config in devicetree.cb and apply macro for
SaGv config for CNL variants boards
Change-Id: If007589d5c1368602928b1550ec8788e65f70c05
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Remove the SmbusEnable parameter from all Cannon Lake mainboards.
Instead this will be determined by the enable state of the SMBUS
PCI device.
Change-Id: I7ece6768da4c517747af12a07012583575816ae1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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generation
This changes uses drivers/intel/wifi chip for CNVi device to ensure that:
1. Correct device name shows in ACPI name space
2. Correct wake up shows in cat /proc/acpi/wakeup
3. Remove cnvi.asl from soc/intel/cannonlake
Change-Id: Ic81de2dce6045ced913766790a40ed19119f5118
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Some of the FSP silicon UPD entry can be updated base on device switch
in pci device tree, have both static config setting and device tree "on"
and "off" will be redundant.
BUG=N/A
TEST=Build and boot up fine with Whiskey Lake RVP platform.
Change-Id: Ia36cfab03c4613786e5580a039d89007b630adf9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27766
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adding common chip config structure which will be used to return data to
common code. When common code requires soc data, code used to fetch
entire soc config structure. With this change, common code will only get
the data/structure which is required by common code and not entire
config.
For now, adding i2c, gspi and lockdown configuration which will be used
by common code.
BUG=none
BRANCH=b:78109109
TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check
values are returned properly using common structure.
Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26189
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.
Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init
Default coreboot does MP initialization for CNL.
Change-Id: Ia7da0842996a9db09e6e2b7b201b3a883c3887a2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch enables S0ix from the devicetree.
Change-Id: I38662dc7203366bdee5f1c7aaa18979867a79ba1
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/25293
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add NHLT and dt support for max98373 amp
BUG=None
TEST=check SSDT and verify entries for max98373
TEST=check NHLT ACPI tables included blobs for max98373
Change-Id: I0b402f89f1ece9e62a394f713c4b0feff29bd1e5
Signed-off-by: N, Harshapriya <harshapriya.n@intel.com>
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/22674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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SATA was enabled only for internal testing. Since we do not use
SATA on chrome platforms, it can be disabled.
Change-Id: I907b440562b39e6d97f604e7e63b6b99e487aaa8
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/22875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Set SCS SD enable FSP parameter and set card detect
gpio information.
Change-Id: Ic99466c0d2d59070418d765442ff6d217023803b
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Leaving the wifi related gpios unmodified for now
due to FSP problem. If H0-H3 is configured as native mode
and GPIORXDIS, GPIOTXDIS bits in DW0 are cleared, it causes
FSP to assert when wifi module is attached. coreboot gpio
macros clears these 2 bits because they are suppose to be
"don't care" in native mode.
TEST=Boot to OS and verify wifi
Change-Id: Ica5e1c43802d04a9471cdfa0087e86f669122fff
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22094
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch provides configuration parameter to enable/disable
Intel Speed Shift Technology.
Change-Id: I95a240e8be6e19ac0e14698ab33543c491a8c974
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/22049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Enable Audio DSP by default on cannonlake rvp platform.
TEST=Boot up into OS and check Audio driver debug print.
Change-Id: I6892c6d349019550c967ef30b84d385f396fc388
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Define PCI express clock usage for cannonlake u and cannonlake y rvp
based on board design.
TEST=Bootable into OS.
Change-Id: I7d71d9a87d87ce6a3e3270f67518afdd54a48db4
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Set SCS emmc HS400 enable FSP parameter.
TEST=Boot to OS, verify HS400 SDHCI print
Change-Id: I3ef8a6740ef985a0c51115d9b0ea753b5db2c70d
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22008
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
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Turn on PCIe express port 9 of PCIe controller 3,
to enable NVMe SSD via M.2 socket 3 on RVP board.
TEST=Boot to OS using Intel NVMe SSD Pro 6
Change-Id: I2fd1cdcf2d9718bf2042262b0c9813811a706b4a
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21908
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set sata enable FSP parameters.
Change-Id: Ie4723b37f0a2028d22f0a344e45a1ded51deecd0
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21407
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure USB2, USB3 and Type-C ports for CannonLake-U RVP
Change-Id: Id875063721ccb62ad4b5187c81f6abf44bf93f74
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Set SCS emmc enable FSP parameter.
Change-Id: Ib3d7a305c3bede439249204cf14d50e3eb8b6915
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21409
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
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Set SMBus, SAGV and Skip FSP MPInit configuration from devicetree.cb
Change-Id: Ic810b003bf7fb13447d5d5dcd49cfcc31785b440
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add gpio pins configuration for cannonlake rvp u/y boards.
Change-Id: Ia077a070979401fe7bd23bda110d2b66a038d9fc
Signed-off-by: john zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Define and populate PCI devices in devicetree for CNL-U RVP
Change-Id: Id04f5efe77a04c180b5dd392da777195bd9fb7a3
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Add both Cannonlake U DDR4 RVP and Cannonlake Y LPDDR4 RVP support.
Implement SPD entry to FSPM for both platforms, seperated platform
specific DQ/DQS/Rcomp input to FSPM as well.
Change-Id: If71662353ddba89a9e831503a2d80dd5ebd65de3
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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