coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2018-11-23	mb: Set coreboot as DSDT's manufacturer model ID	Elyes HAOUAS
	Field 'OEMID' & "OEM Table ID" are related to DSDT table not to mainboard. So use macro to set them respectvely to "COREv4" and "COREBOOT". Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian
2018-11-21	ACPI: Fix DSDT's revision field	Elyes HAOUAS
	DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version. This will cause the AML interpreter to use 32-bit integers and math if the version is 1, and 64-bit if the version is >=2. Current spec version is 2 for ACPI 6.2-a. Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29626 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-20	soc/intel/cannonlake: Add platform.asl	Lijian Zhao
	Include common platform.asl to have generic indication of power transition state of system. TEST=Enter and resume from S3, check the post code had been changed to 0096 and 0097. Change-Id: Ic38ac6d7e60441caeba5c088c9dbe4d901355782 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22111 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-12	mainboard/intel/cannonlake_rvp: Add Sleep states	Vaibhav Shankar
	Add sleep state to DSDT table. Change-Id: Ic14e34e29d5f881949765dee5c6b433c1499c491 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/21976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-09-19	mainboard/intel/cannonlake_rvp: Add PCI, PCIE IRQs to DSDT table	Bora Guvendik
	Change-Id: Id0b2b9e9ae2755ed89cee337a1a085fc4e95b073 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13	mainboard/intel/cannonlake_rvp: Add dummy DSDT table	Lijian Zhao
	Add dummy ACPI DSDT table for cannonlake rvp platform. Change-Id: If45c2a7da7f5b20ddd3d56bf9d7f68a85d2f791d Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06	Revert "soc/intel/cannonlake: Add dummy ACPI DSDT table"	Kyösti Mälkki
	This reverts commit 6c0f3c7ee1d53872851dbab636787852e3572c98. Reason for revert: Broke master builds, this was submitted out-of-order, some of the dependencies have not passed review with +2 yet. Change-Id: Ib7bcb1b98623d16e074caeca839a936d71ded709 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2017-09-06	soc/intel/cannonlake: Add dummy ACPI DSDT table	Lijian Zhao
	A dummy DSDT table will be created for cannonlake. Change-Id: Ia435f2a03982313c6b0c63ac25668a3300d08793 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>